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30 package s390x
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "fmt"
36 "log"
37 "math"
38 "slices"
39 )
40
41
42
43
44 type ctxtz struct {
45 ctxt *obj.Link
46 newprog obj.ProgAlloc
47 cursym *obj.LSym
48 autosize int32
49 instoffset int64
50 pc int64
51 }
52
53
54 const (
55 funcAlign = 16
56 )
57
58 type Optab struct {
59 as obj.As
60 i uint8
61 a1 uint8
62 a2 uint8
63 a3 uint8
64 a4 uint8
65 a5 uint8
66 a6 uint8
67 }
68
69 var optab = []Optab{
70
71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
75 {i: 0, as: obj.ANOP},
76 {i: 0, as: obj.ANOP, a1: C_SAUTO},
77
78
79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
86
87
88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
96
97
98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
118
119
120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
139
140
141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
160
161
162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
163
164
165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
166 {i: 2, as: AADD, a1: C_REG, a6: C_REG},
167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG},
169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
177 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG},
178 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
179 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
180 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
181 {i: 10, as: ASUB, a1: C_REG, a6: C_REG},
182 {i: 47, as: ANEG, a1: C_REG, a6: C_REG},
183 {i: 47, as: ANEG, a6: C_REG},
184
185
186 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
187 {i: 6, as: AAND, a1: C_REG, a6: C_REG},
188 {i: 23, as: AAND, a1: C_LCON, a6: C_REG},
189 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
190 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
191 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
192 {i: 6, as: AANDW, a1: C_REG, a6: C_REG},
193 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
194 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
195 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
196 {i: 7, as: ASLD, a1: C_REG, a6: C_REG},
197 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
198 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
199 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
200 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
201
202
203 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
204
205
206 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
207 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
208 {i: 33, as: AFABS, a6: C_FREG},
209 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
210 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
211 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
212 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
213 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
216 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
217 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
218 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
219 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
220 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
221 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
222 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
223 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
224 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
225 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
226
227
228 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
229 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
230 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
231 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
232
233
234 {i: 5, as: ASYSCALL},
235 {i: 77, as: ASYSCALL, a1: C_SCON},
236
237
238 {i: 16, as: ABEQ, a6: C_SBRA},
239 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA},
240 {i: 11, as: ABR, a6: C_LBRA},
241 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
242 {i: 18, as: ABR, a6: C_REG},
243 {i: 18, as: ABR, a1: C_REG, a6: C_REG},
244 {i: 15, as: ABR, a6: C_ZOREG},
245 {i: 15, as: ABC, a6: C_ZOREG},
246
247
248 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
249 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
250 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
251 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
252 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA},
254 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
256 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
257 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
258
259
260 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA},
261 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA},
262
263
264 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
265
266
267 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG},
268
269
270 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
271
272
273 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
274
275
276 {i: 70, as: ACMP, a1: C_REG, a6: C_REG},
277 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
278 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
279 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
280 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
281 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
282
283
284 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
285
286
287 {i: 92, as: AIPM, a1: C_REG},
288
289
290 {i: 76, as: ASPM, a1: C_REG},
291
292
293 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
294 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
295 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
296 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
297
298
299 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
301
302
303 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
305 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
306 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
307
308
309 {i: 40, as: ABYTE, a1: C_SCON},
310 {i: 40, as: AWORD, a1: C_LCON},
311 {i: 31, as: ADWORD, a1: C_LCON},
312 {i: 31, as: ADWORD, a1: C_DCON},
313
314
315 {i: 80, as: ASYNC},
316
317
318 {i: 88, as: ASTCK, a6: C_SAUTO},
319 {i: 88, as: ASTCK, a6: C_SOREG},
320
321
322 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
325
326
327 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
328 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
329 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
330 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
331 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
332
333
334 {i: 78, as: obj.AUNDEF},
335
336
337 {i: 73, as: ABRRK},
338
339
340 {i: 66, as: ANOPH},
341
342
343
344
345 {i: 124, as: AKM, a1: C_REG, a6: C_REG},
346
347
348 {i: 125, as: AKDSA, a1: C_REG, a6: C_REG},
349
350
351 {i: 126, as: AKMA, a1: C_REG, a2: C_REG, a6: C_REG},
352
353
354
355
356 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
357 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
358 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
359 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
360
361
362 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
363 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
364 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
365 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
366
367
368 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
369 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
370
371
372 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
373 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
374
375
376 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
377 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
378 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
379 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
380 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
381 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
382 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
383 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
384
385
386 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
387 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
388
389
390 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
391 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
392
393
394 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
395 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
396
397
398 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
399 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
400
401
402 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
403 {i: 109, as: AVZERO, a6: C_VREG},
404 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
405 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
406 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
407 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
408
409
410 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
411
412
413 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
414
415
416
417 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
418 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
419
420
421 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
422
423
424 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
425
426
427 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
428
429
430 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
431 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
432 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
433
434
435 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
436 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
437 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
438 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
439
440
441 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
442 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
443
444
445 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
446
447
448 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
449
450
451 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
452
453
454 {i: 127, as: AMVCLE, a1: C_LOREG, a2: C_REG, a6: C_REG},
455 {i: 127, as: AMVCLE, a1: C_SCON, a2: C_REG, a6: C_REG},
456 }
457
458 var oprange [ALAST & obj.AMask][]Optab
459
460 var xcmp [C_NCLASS][C_NCLASS]bool
461
462 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
463 if ctxt.Retpoline {
464 ctxt.Diag("-spectre=ret not supported on s390x")
465 ctxt.Retpoline = false
466 }
467
468 p := cursym.Func().Text
469 if p == nil || p.Link == nil {
470 return
471 }
472
473 if oprange[AORW&obj.AMask] == nil {
474 ctxt.Diag("s390x ops not initialized, call s390x.buildop first")
475 }
476
477 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
478
479 buffer := make([]byte, 0)
480 changed := true
481 loop := 0
482 nrelocs0 := len(c.cursym.R)
483 for changed {
484 if loop > 100 {
485 c.ctxt.Diag("stuck in spanz loop")
486 break
487 }
488 changed = false
489 buffer = buffer[:0]
490 for i := range c.cursym.R[nrelocs0:] {
491 c.cursym.R[nrelocs0+i] = obj.Reloc{}
492 }
493 c.cursym.R = c.cursym.R[:nrelocs0]
494 for p := c.cursym.Func().Text; p != nil; p = p.Link {
495 pc := int64(len(buffer))
496 if pc != p.Pc {
497 changed = true
498 }
499 p.Pc = pc
500 c.pc = p.Pc
501 c.asmout(p, &buffer)
502 if pc == int64(len(buffer)) {
503 switch p.As {
504 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
505
506 default:
507 c.ctxt.Diag("zero-width instruction\n%v", p)
508 }
509 }
510 }
511 loop++
512 }
513
514 c.cursym.Size = int64(len(buffer))
515 if c.cursym.Size%funcAlign != 0 {
516 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign)
517 }
518 c.cursym.Grow(c.cursym.Size)
519 copy(c.cursym.P, buffer)
520
521
522
523
524
525 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, nil)
526 }
527
528
529 func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool {
530 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP {
531 return true
532 }
533 for _, a := range p.RestArgs {
534 if a.Reg == REGTMP {
535 return true
536 }
537 }
538 return p.Mark&USETMP != 0
539 }
540
541 func isint32(v int64) bool {
542 return int64(int32(v)) == v
543 }
544
545 func isuint32(v uint64) bool {
546 return uint64(uint32(v)) == v
547 }
548
549 func (c *ctxtz) aclass(a *obj.Addr) int {
550 switch a.Type {
551 case obj.TYPE_NONE:
552 return C_NONE
553
554 case obj.TYPE_REG:
555 if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
556 return C_REG
557 }
558 if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
559 return C_FREG
560 }
561 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
562 return C_AREG
563 }
564 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
565 return C_VREG
566 }
567 return C_GOK
568
569 case obj.TYPE_MEM:
570 switch a.Name {
571 case obj.NAME_EXTERN,
572 obj.NAME_STATIC:
573 if a.Sym == nil {
574
575 break
576 }
577 c.instoffset = a.Offset
578 if a.Sym.Type == objabi.STLSBSS {
579 if c.ctxt.Flag_shared {
580 return C_TLS_IE
581 }
582 return C_TLS_LE
583 }
584 return C_ADDR
585
586 case obj.NAME_GOTREF:
587 return C_GOTADDR
588
589 case obj.NAME_AUTO:
590 if a.Reg == REGSP {
591
592
593 a.Reg = obj.REG_NONE
594 }
595 c.instoffset = int64(c.autosize) + a.Offset
596 if c.instoffset >= -BIG && c.instoffset < BIG {
597 return C_SAUTO
598 }
599 return C_LAUTO
600
601 case obj.NAME_PARAM:
602 if a.Reg == REGSP {
603
604
605 a.Reg = obj.REG_NONE
606 }
607 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
608 if c.instoffset >= -BIG && c.instoffset < BIG {
609 return C_SAUTO
610 }
611 return C_LAUTO
612
613 case obj.NAME_NONE:
614 c.instoffset = a.Offset
615 if c.instoffset == 0 {
616 return C_ZOREG
617 }
618 if c.instoffset >= -BIG && c.instoffset < BIG {
619 return C_SOREG
620 }
621 return C_LOREG
622 }
623
624 return C_GOK
625
626 case obj.TYPE_TEXTSIZE:
627 return C_TEXTSIZE
628
629 case obj.TYPE_FCONST:
630 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
631 return C_ZCON
632 }
633 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val)
634
635 case obj.TYPE_CONST,
636 obj.TYPE_ADDR:
637 switch a.Name {
638 case obj.NAME_NONE:
639 c.instoffset = a.Offset
640 if a.Reg != 0 {
641 if -BIG <= c.instoffset && c.instoffset <= BIG {
642 return C_SACON
643 }
644 if isint32(c.instoffset) {
645 return C_LACON
646 }
647 return C_DACON
648 }
649
650 case obj.NAME_EXTERN,
651 obj.NAME_STATIC:
652 s := a.Sym
653 if s == nil {
654 return C_GOK
655 }
656 c.instoffset = a.Offset
657
658 return C_SYMADDR
659
660 case obj.NAME_AUTO:
661 if a.Reg == REGSP {
662
663
664 a.Reg = obj.REG_NONE
665 }
666 c.instoffset = int64(c.autosize) + a.Offset
667 if c.instoffset >= -BIG && c.instoffset < BIG {
668 return C_SACON
669 }
670 return C_LACON
671
672 case obj.NAME_PARAM:
673 if a.Reg == REGSP {
674
675
676 a.Reg = obj.REG_NONE
677 }
678 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
679 if c.instoffset >= -BIG && c.instoffset < BIG {
680 return C_SACON
681 }
682 return C_LACON
683
684 default:
685 return C_GOK
686 }
687
688 if c.instoffset == 0 {
689 return C_ZCON
690 }
691 if c.instoffset >= 0 {
692 if c.instoffset <= 0x7fff {
693 return C_SCON
694 }
695 if c.instoffset <= 0xffff {
696 return C_ANDCON
697 }
698 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) {
699 return C_UCON
700 }
701 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
702 return C_LCON
703 }
704 return C_DCON
705 }
706
707 if c.instoffset >= -0x8000 {
708 return C_ADDCON
709 }
710 if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
711 return C_UCON
712 }
713 if isint32(c.instoffset) {
714 return C_LCON
715 }
716 return C_DCON
717
718 case obj.TYPE_BRANCH:
719 return C_SBRA
720 }
721
722 return C_GOK
723 }
724
725 func (c *ctxtz) oplook(p *obj.Prog) *Optab {
726
727 if p.Optab != 0 {
728 return &optab[p.Optab-1]
729 }
730 if len(p.RestArgs) > 3 {
731 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs))
732 return nil
733 }
734
735
736 p.From.Class = int8(c.aclass(&p.From) + 1)
737 p.To.Class = int8(c.aclass(&p.To) + 1)
738 for i := range p.RestArgs {
739 p.RestArgs[i].Addr.Class = int8(c.aclass(&p.RestArgs[i].Addr) + 1)
740 }
741
742
743 args := [...]int8{
744 p.From.Class - 1,
745 C_NONE,
746 C_NONE,
747 C_NONE,
748 C_NONE,
749 p.To.Class - 1,
750 }
751
752 switch {
753 case REG_R0 <= p.Reg && p.Reg <= REG_R15:
754 args[1] = C_REG
755 case REG_V0 <= p.Reg && p.Reg <= REG_V31:
756 args[1] = C_VREG
757 case REG_F0 <= p.Reg && p.Reg <= REG_F15:
758 args[1] = C_FREG
759 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15:
760 args[1] = C_AREG
761 }
762
763 for i, a := range p.RestArgs {
764 args[2+i] = a.Class - 1
765 }
766
767
768 ops := oprange[p.As&obj.AMask]
769 cmp := [len(args)]*[C_NCLASS]bool{}
770 for i := range cmp {
771 cmp[i] = &xcmp[args[i]]
772 }
773 for i := range ops {
774 op := &ops[i]
775 if cmp[0][op.a1] && cmp[1][op.a2] &&
776 cmp[2][op.a3] && cmp[3][op.a4] &&
777 cmp[4][op.a5] && cmp[5][op.a6] {
778 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
779 return op
780 }
781 }
782
783
784 s := ""
785 for _, a := range args {
786 s += fmt.Sprintf(" %v", DRconv(int(a)))
787 }
788 c.ctxt.Diag("illegal combination %v%v\n", p.As, s)
789 c.ctxt.Diag("prog: %v\n", p)
790 return nil
791 }
792
793 func cmp(a int, b int) bool {
794 if a == b {
795 return true
796 }
797 switch a {
798 case C_DCON:
799 if b == C_LCON {
800 return true
801 }
802 fallthrough
803 case C_LCON:
804 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
805 return true
806 }
807
808 case C_ADDCON:
809 if b == C_ZCON || b == C_SCON {
810 return true
811 }
812
813 case C_ANDCON:
814 if b == C_ZCON || b == C_SCON {
815 return true
816 }
817
818 case C_UCON:
819 if b == C_ZCON || b == C_SCON {
820 return true
821 }
822
823 case C_SCON:
824 if b == C_ZCON {
825 return true
826 }
827
828 case C_LACON:
829 if b == C_SACON {
830 return true
831 }
832
833 case C_LBRA:
834 if b == C_SBRA {
835 return true
836 }
837
838 case C_LAUTO:
839 if b == C_SAUTO {
840 return true
841 }
842
843 case C_LOREG:
844 if b == C_ZOREG || b == C_SOREG {
845 return true
846 }
847
848 case C_SOREG:
849 if b == C_ZOREG {
850 return true
851 }
852
853 case C_ANY:
854 return true
855 }
856
857 return false
858 }
859
860 func ocmp(p1, p2 Optab) int {
861 if p1.as != p2.as {
862 return int(p1.as) - int(p2.as)
863 }
864 if p1.a1 != p2.a1 {
865 return int(p1.a1) - int(p2.a1)
866 }
867 if p1.a2 != p2.a2 {
868 return int(p1.a2) - int(p2.a2)
869 }
870 if p1.a3 != p2.a3 {
871 return int(p1.a3) - int(p2.a3)
872 }
873 if p1.a4 != p2.a4 {
874 return int(p1.a4) - int(p2.a4)
875 }
876 return 0
877 }
878 func opset(a, b obj.As) {
879 oprange[a&obj.AMask] = oprange[b&obj.AMask]
880 }
881
882 func buildop(ctxt *obj.Link) {
883 if oprange[AORW&obj.AMask] != nil {
884
885
886
887 return
888 }
889
890 for i := 0; i < C_NCLASS; i++ {
891 for n := 0; n < C_NCLASS; n++ {
892 if cmp(n, i) {
893 xcmp[i][n] = true
894 }
895 }
896 }
897 slices.SortFunc(optab, ocmp)
898 for i := 0; i < len(optab); i++ {
899 r := optab[i].as
900 start := i
901 for ; i+1 < len(optab); i++ {
902 if optab[i+1].as != r {
903 break
904 }
905 }
906 oprange[r&obj.AMask] = optab[start : i+1]
907
908
909
910 switch r {
911 case AADD:
912 opset(AADDC, r)
913 opset(AADDW, r)
914 opset(AADDE, r)
915 opset(AMULLD, r)
916 opset(AMULLW, r)
917 case ADIVW:
918 opset(ADIVD, r)
919 opset(ADIVDU, r)
920 opset(ADIVWU, r)
921 opset(AMODD, r)
922 opset(AMODDU, r)
923 opset(AMODW, r)
924 opset(AMODWU, r)
925 case AMULHD:
926 opset(AMULHDU, r)
927 case AMOVBZ:
928 opset(AMOVH, r)
929 opset(AMOVHZ, r)
930 case ALA:
931 opset(ALAY, r)
932 case AMVC:
933 opset(AMVCIN, r)
934 opset(ACLC, r)
935 opset(AXC, r)
936 opset(AOC, r)
937 opset(ANC, r)
938 case ASTCK:
939 opset(ASTCKC, r)
940 opset(ASTCKE, r)
941 opset(ASTCKF, r)
942 case ALAAG:
943 opset(ALAA, r)
944 opset(ALAAL, r)
945 opset(ALAALG, r)
946 opset(ALAN, r)
947 opset(ALANG, r)
948 opset(ALAX, r)
949 opset(ALAXG, r)
950 opset(ALAO, r)
951 opset(ALAOG, r)
952 case ASTMG:
953 opset(ASTMY, r)
954 case ALMG:
955 opset(ALMY, r)
956 case ABEQ:
957 opset(ABGE, r)
958 opset(ABGT, r)
959 opset(ABLE, r)
960 opset(ABLT, r)
961 opset(ABNE, r)
962 opset(ABVC, r)
963 opset(ABVS, r)
964 opset(ABLEU, r)
965 opset(ABLTU, r)
966 case ABR:
967 opset(ABL, r)
968 case ABC:
969 opset(ABCL, r)
970 case AFABS:
971 opset(AFNABS, r)
972 opset(ALPDFR, r)
973 opset(ALNDFR, r)
974 opset(AFNEG, r)
975 opset(AFNEGS, r)
976 opset(ALCDBR, r)
977 opset(ALEDBR, r)
978 opset(ALDEBR, r)
979 opset(AFSQRT, r)
980 opset(AFSQRTS, r)
981 case AFADD:
982 opset(AFADDS, r)
983 opset(AFDIV, r)
984 opset(AFDIVS, r)
985 opset(AFSUB, r)
986 opset(AFSUBS, r)
987 case AFMADD:
988 opset(AFMADDS, r)
989 opset(AFMSUB, r)
990 opset(AFMSUBS, r)
991 case AFMUL:
992 opset(AFMULS, r)
993 case AFCMPO:
994 opset(AFCMPU, r)
995 opset(ACEBR, r)
996 case AAND:
997 opset(AOR, r)
998 opset(AXOR, r)
999 case AANDW:
1000 opset(AORW, r)
1001 opset(AXORW, r)
1002 case ASLD:
1003 opset(ASRD, r)
1004 opset(ASLW, r)
1005 opset(ASRW, r)
1006 opset(ASRAD, r)
1007 opset(ASRAW, r)
1008 opset(ARLL, r)
1009 opset(ARLLG, r)
1010 case ARNSBG:
1011 opset(ARXSBG, r)
1012 opset(AROSBG, r)
1013 opset(ARNSBGT, r)
1014 opset(ARXSBGT, r)
1015 opset(AROSBGT, r)
1016 opset(ARISBG, r)
1017 opset(ARISBGN, r)
1018 opset(ARISBGZ, r)
1019 opset(ARISBGNZ, r)
1020 opset(ARISBHG, r)
1021 opset(ARISBLG, r)
1022 opset(ARISBHGZ, r)
1023 opset(ARISBLGZ, r)
1024 case ACSG:
1025 opset(ACS, r)
1026 case ASUB:
1027 opset(ASUBC, r)
1028 opset(ASUBE, r)
1029 opset(ASUBW, r)
1030 case ANEG:
1031 opset(ANEGW, r)
1032 case AFMOVD:
1033 opset(AFMOVS, r)
1034 case AMOVDBR:
1035 opset(AMOVWBR, r)
1036 case ACMP:
1037 opset(ACMPW, r)
1038 case ACMPU:
1039 opset(ACMPWU, r)
1040 case ATMHH:
1041 opset(ATMHL, r)
1042 opset(ATMLH, r)
1043 opset(ATMLL, r)
1044 case ACEFBRA:
1045 opset(ACDFBRA, r)
1046 opset(ACEGBRA, r)
1047 opset(ACDGBRA, r)
1048 opset(ACELFBR, r)
1049 opset(ACDLFBR, r)
1050 opset(ACELGBR, r)
1051 opset(ACDLGBR, r)
1052 case ACFEBRA:
1053 opset(ACFDBRA, r)
1054 opset(ACGEBRA, r)
1055 opset(ACGDBRA, r)
1056 opset(ACLFEBR, r)
1057 opset(ACLFDBR, r)
1058 opset(ACLGEBR, r)
1059 opset(ACLGDBR, r)
1060 case AFIEBR:
1061 opset(AFIDBR, r)
1062 case ACMPBEQ:
1063 opset(ACMPBGE, r)
1064 opset(ACMPBGT, r)
1065 opset(ACMPBLE, r)
1066 opset(ACMPBLT, r)
1067 opset(ACMPBNE, r)
1068 case ACMPUBEQ:
1069 opset(ACMPUBGE, r)
1070 opset(ACMPUBGT, r)
1071 opset(ACMPUBLE, r)
1072 opset(ACMPUBLT, r)
1073 opset(ACMPUBNE, r)
1074 case ACGRJ:
1075 opset(ACRJ, r)
1076 case ACLGRJ:
1077 opset(ACLRJ, r)
1078 case ACGIJ:
1079 opset(ACIJ, r)
1080 case ACLGIJ:
1081 opset(ACLIJ, r)
1082 case AMOVDEQ:
1083 opset(AMOVDGE, r)
1084 opset(AMOVDGT, r)
1085 opset(AMOVDLE, r)
1086 opset(AMOVDLT, r)
1087 opset(AMOVDNE, r)
1088 case ALOCGR:
1089 opset(ALOCR, r)
1090 case ALTDBR:
1091 opset(ALTEBR, r)
1092 case ATCDB:
1093 opset(ATCEB, r)
1094 case AVL:
1095 opset(AVLLEZB, r)
1096 opset(AVLLEZH, r)
1097 opset(AVLLEZF, r)
1098 opset(AVLLEZG, r)
1099 opset(AVLREPB, r)
1100 opset(AVLREPH, r)
1101 opset(AVLREPF, r)
1102 opset(AVLREPG, r)
1103 case AVLEG:
1104 opset(AVLBB, r)
1105 opset(AVLEB, r)
1106 opset(AVLEH, r)
1107 opset(AVLEF, r)
1108 opset(AVLEG, r)
1109 opset(AVLREP, r)
1110 case AVSTEG:
1111 opset(AVSTEB, r)
1112 opset(AVSTEH, r)
1113 opset(AVSTEF, r)
1114 case AVSCEG:
1115 opset(AVSCEF, r)
1116 case AVGEG:
1117 opset(AVGEF, r)
1118 case AVESLG:
1119 opset(AVESLB, r)
1120 opset(AVESLH, r)
1121 opset(AVESLF, r)
1122 opset(AVERLLB, r)
1123 opset(AVERLLH, r)
1124 opset(AVERLLF, r)
1125 opset(AVERLLG, r)
1126 opset(AVESRAB, r)
1127 opset(AVESRAH, r)
1128 opset(AVESRAF, r)
1129 opset(AVESRAG, r)
1130 opset(AVESRLB, r)
1131 opset(AVESRLH, r)
1132 opset(AVESRLF, r)
1133 opset(AVESRLG, r)
1134 case AVLGVG:
1135 opset(AVLGVB, r)
1136 opset(AVLGVH, r)
1137 opset(AVLGVF, r)
1138 case AVLVGG:
1139 opset(AVLVGB, r)
1140 opset(AVLVGH, r)
1141 opset(AVLVGF, r)
1142 case AVZERO:
1143 opset(AVONE, r)
1144 case AVREPIG:
1145 opset(AVREPIB, r)
1146 opset(AVREPIH, r)
1147 opset(AVREPIF, r)
1148 case AVLEIG:
1149 opset(AVLEIB, r)
1150 opset(AVLEIH, r)
1151 opset(AVLEIF, r)
1152 case AVGMG:
1153 opset(AVGMB, r)
1154 opset(AVGMH, r)
1155 opset(AVGMF, r)
1156 case AVREPG:
1157 opset(AVREPB, r)
1158 opset(AVREPH, r)
1159 opset(AVREPF, r)
1160 case AVERIMG:
1161 opset(AVERIMB, r)
1162 opset(AVERIMH, r)
1163 opset(AVERIMF, r)
1164 case AVFTCIDB:
1165 opset(AWFTCIDB, r)
1166 case AVLR:
1167 opset(AVUPHB, r)
1168 opset(AVUPHH, r)
1169 opset(AVUPHF, r)
1170 opset(AVUPLHB, r)
1171 opset(AVUPLHH, r)
1172 opset(AVUPLHF, r)
1173 opset(AVUPLB, r)
1174 opset(AVUPLHW, r)
1175 opset(AVUPLF, r)
1176 opset(AVUPLLB, r)
1177 opset(AVUPLLH, r)
1178 opset(AVUPLLF, r)
1179 opset(AVCLZB, r)
1180 opset(AVCLZH, r)
1181 opset(AVCLZF, r)
1182 opset(AVCLZG, r)
1183 opset(AVCTZB, r)
1184 opset(AVCTZH, r)
1185 opset(AVCTZF, r)
1186 opset(AVCTZG, r)
1187 opset(AVLDEB, r)
1188 opset(AWLDEB, r)
1189 opset(AVFLCDB, r)
1190 opset(AWFLCDB, r)
1191 opset(AVFLNDB, r)
1192 opset(AWFLNDB, r)
1193 opset(AVFLPDB, r)
1194 opset(AWFLPDB, r)
1195 opset(AVFSQDB, r)
1196 opset(AWFSQDB, r)
1197 opset(AVISTRB, r)
1198 opset(AVISTRH, r)
1199 opset(AVISTRF, r)
1200 opset(AVISTRBS, r)
1201 opset(AVISTRHS, r)
1202 opset(AVISTRFS, r)
1203 opset(AVLCB, r)
1204 opset(AVLCH, r)
1205 opset(AVLCF, r)
1206 opset(AVLCG, r)
1207 opset(AVLPB, r)
1208 opset(AVLPH, r)
1209 opset(AVLPF, r)
1210 opset(AVLPG, r)
1211 opset(AVPOPCT, r)
1212 opset(AVSEGB, r)
1213 opset(AVSEGH, r)
1214 opset(AVSEGF, r)
1215 case AVECG:
1216 opset(AVECB, r)
1217 opset(AVECH, r)
1218 opset(AVECF, r)
1219 opset(AVECLB, r)
1220 opset(AVECLH, r)
1221 opset(AVECLF, r)
1222 opset(AVECLG, r)
1223 opset(AWFCDB, r)
1224 opset(AWFKDB, r)
1225 case AVCEQG:
1226 opset(AVCEQB, r)
1227 opset(AVCEQH, r)
1228 opset(AVCEQF, r)
1229 opset(AVCEQBS, r)
1230 opset(AVCEQHS, r)
1231 opset(AVCEQFS, r)
1232 opset(AVCEQGS, r)
1233 opset(AVCHB, r)
1234 opset(AVCHH, r)
1235 opset(AVCHF, r)
1236 opset(AVCHG, r)
1237 opset(AVCHBS, r)
1238 opset(AVCHHS, r)
1239 opset(AVCHFS, r)
1240 opset(AVCHGS, r)
1241 opset(AVCHLB, r)
1242 opset(AVCHLH, r)
1243 opset(AVCHLF, r)
1244 opset(AVCHLG, r)
1245 opset(AVCHLBS, r)
1246 opset(AVCHLHS, r)
1247 opset(AVCHLFS, r)
1248 opset(AVCHLGS, r)
1249 case AVFAEF:
1250 opset(AVFAEB, r)
1251 opset(AVFAEH, r)
1252 opset(AVFAEBS, r)
1253 opset(AVFAEHS, r)
1254 opset(AVFAEFS, r)
1255 opset(AVFAEZB, r)
1256 opset(AVFAEZH, r)
1257 opset(AVFAEZF, r)
1258 opset(AVFAEZBS, r)
1259 opset(AVFAEZHS, r)
1260 opset(AVFAEZFS, r)
1261 opset(AVFEEB, r)
1262 opset(AVFEEH, r)
1263 opset(AVFEEF, r)
1264 opset(AVFEEBS, r)
1265 opset(AVFEEHS, r)
1266 opset(AVFEEFS, r)
1267 opset(AVFEEZB, r)
1268 opset(AVFEEZH, r)
1269 opset(AVFEEZF, r)
1270 opset(AVFEEZBS, r)
1271 opset(AVFEEZHS, r)
1272 opset(AVFEEZFS, r)
1273 opset(AVFENEB, r)
1274 opset(AVFENEH, r)
1275 opset(AVFENEF, r)
1276 opset(AVFENEBS, r)
1277 opset(AVFENEHS, r)
1278 opset(AVFENEFS, r)
1279 opset(AVFENEZB, r)
1280 opset(AVFENEZH, r)
1281 opset(AVFENEZF, r)
1282 opset(AVFENEZBS, r)
1283 opset(AVFENEZHS, r)
1284 opset(AVFENEZFS, r)
1285 case AVPKSG:
1286 opset(AVPKSH, r)
1287 opset(AVPKSF, r)
1288 opset(AVPKSHS, r)
1289 opset(AVPKSFS, r)
1290 opset(AVPKSGS, r)
1291 opset(AVPKLSH, r)
1292 opset(AVPKLSF, r)
1293 opset(AVPKLSG, r)
1294 opset(AVPKLSHS, r)
1295 opset(AVPKLSFS, r)
1296 opset(AVPKLSGS, r)
1297 case AVAQ:
1298 opset(AVAB, r)
1299 opset(AVAH, r)
1300 opset(AVAF, r)
1301 opset(AVAG, r)
1302 opset(AVACCB, r)
1303 opset(AVACCH, r)
1304 opset(AVACCF, r)
1305 opset(AVACCG, r)
1306 opset(AVACCQ, r)
1307 opset(AVN, r)
1308 opset(AVNC, r)
1309 opset(AVAVGB, r)
1310 opset(AVAVGH, r)
1311 opset(AVAVGF, r)
1312 opset(AVAVGG, r)
1313 opset(AVAVGLB, r)
1314 opset(AVAVGLH, r)
1315 opset(AVAVGLF, r)
1316 opset(AVAVGLG, r)
1317 opset(AVCKSM, r)
1318 opset(AVX, r)
1319 opset(AVFADB, r)
1320 opset(AWFADB, r)
1321 opset(AVFCEDB, r)
1322 opset(AVFCEDBS, r)
1323 opset(AWFCEDB, r)
1324 opset(AWFCEDBS, r)
1325 opset(AVFCHDB, r)
1326 opset(AVFCHDBS, r)
1327 opset(AWFCHDB, r)
1328 opset(AWFCHDBS, r)
1329 opset(AVFCHEDB, r)
1330 opset(AVFCHEDBS, r)
1331 opset(AWFCHEDB, r)
1332 opset(AWFCHEDBS, r)
1333 opset(AVFMDB, r)
1334 opset(AWFMDB, r)
1335 opset(AVGFMB, r)
1336 opset(AVGFMH, r)
1337 opset(AVGFMF, r)
1338 opset(AVGFMG, r)
1339 opset(AVMXB, r)
1340 opset(AVMXH, r)
1341 opset(AVMXF, r)
1342 opset(AVMXG, r)
1343 opset(AVMXLB, r)
1344 opset(AVMXLH, r)
1345 opset(AVMXLF, r)
1346 opset(AVMXLG, r)
1347 opset(AVMNB, r)
1348 opset(AVMNH, r)
1349 opset(AVMNF, r)
1350 opset(AVMNG, r)
1351 opset(AVMNLB, r)
1352 opset(AVMNLH, r)
1353 opset(AVMNLF, r)
1354 opset(AVMNLG, r)
1355 opset(AVMRHB, r)
1356 opset(AVMRHH, r)
1357 opset(AVMRHF, r)
1358 opset(AVMRHG, r)
1359 opset(AVMRLB, r)
1360 opset(AVMRLH, r)
1361 opset(AVMRLF, r)
1362 opset(AVMRLG, r)
1363 opset(AVMEB, r)
1364 opset(AVMEH, r)
1365 opset(AVMEF, r)
1366 opset(AVMLEB, r)
1367 opset(AVMLEH, r)
1368 opset(AVMLEF, r)
1369 opset(AVMOB, r)
1370 opset(AVMOH, r)
1371 opset(AVMOF, r)
1372 opset(AVMLOB, r)
1373 opset(AVMLOH, r)
1374 opset(AVMLOF, r)
1375 opset(AVMHB, r)
1376 opset(AVMHH, r)
1377 opset(AVMHF, r)
1378 opset(AVMLHB, r)
1379 opset(AVMLHH, r)
1380 opset(AVMLHF, r)
1381 opset(AVMLH, r)
1382 opset(AVMLHW, r)
1383 opset(AVMLF, r)
1384 opset(AVNO, r)
1385 opset(AVO, r)
1386 opset(AVPKH, r)
1387 opset(AVPKF, r)
1388 opset(AVPKG, r)
1389 opset(AVSUMGH, r)
1390 opset(AVSUMGF, r)
1391 opset(AVSUMQF, r)
1392 opset(AVSUMQG, r)
1393 opset(AVSUMB, r)
1394 opset(AVSUMH, r)
1395 case AVERLLVG:
1396 opset(AVERLLVB, r)
1397 opset(AVERLLVH, r)
1398 opset(AVERLLVF, r)
1399 opset(AVESLVB, r)
1400 opset(AVESLVH, r)
1401 opset(AVESLVF, r)
1402 opset(AVESLVG, r)
1403 opset(AVESRAVB, r)
1404 opset(AVESRAVH, r)
1405 opset(AVESRAVF, r)
1406 opset(AVESRAVG, r)
1407 opset(AVESRLVB, r)
1408 opset(AVESRLVH, r)
1409 opset(AVESRLVF, r)
1410 opset(AVESRLVG, r)
1411 opset(AVFDDB, r)
1412 opset(AWFDDB, r)
1413 opset(AVFSDB, r)
1414 opset(AWFSDB, r)
1415 opset(AVSL, r)
1416 opset(AVSLB, r)
1417 opset(AVSRA, r)
1418 opset(AVSRAB, r)
1419 opset(AVSRL, r)
1420 opset(AVSRLB, r)
1421 opset(AVSB, r)
1422 opset(AVSH, r)
1423 opset(AVSF, r)
1424 opset(AVSG, r)
1425 opset(AVSQ, r)
1426 opset(AVSCBIB, r)
1427 opset(AVSCBIH, r)
1428 opset(AVSCBIF, r)
1429 opset(AVSCBIG, r)
1430 opset(AVSCBIQ, r)
1431 case AVACQ:
1432 opset(AVACCCQ, r)
1433 opset(AVGFMAB, r)
1434 opset(AVGFMAH, r)
1435 opset(AVGFMAF, r)
1436 opset(AVGFMAG, r)
1437 opset(AVMALB, r)
1438 opset(AVMALHW, r)
1439 opset(AVMALF, r)
1440 opset(AVMAHB, r)
1441 opset(AVMAHH, r)
1442 opset(AVMAHF, r)
1443 opset(AVMALHB, r)
1444 opset(AVMALHH, r)
1445 opset(AVMALHF, r)
1446 opset(AVMAEB, r)
1447 opset(AVMAEH, r)
1448 opset(AVMAEF, r)
1449 opset(AVMALEB, r)
1450 opset(AVMALEH, r)
1451 opset(AVMALEF, r)
1452 opset(AVMAOB, r)
1453 opset(AVMAOH, r)
1454 opset(AVMAOF, r)
1455 opset(AVMALOB, r)
1456 opset(AVMALOH, r)
1457 opset(AVMALOF, r)
1458 opset(AVSTRC, r)
1459 opset(AVSTRCB, r)
1460 opset(AVSTRCH, r)
1461 opset(AVSTRCF, r)
1462 opset(AVSTRCBS, r)
1463 opset(AVSTRCHS, r)
1464 opset(AVSTRCFS, r)
1465 opset(AVSTRCZB, r)
1466 opset(AVSTRCZH, r)
1467 opset(AVSTRCZF, r)
1468 opset(AVSTRCZBS, r)
1469 opset(AVSTRCZHS, r)
1470 opset(AVSTRCZFS, r)
1471 opset(AVSBCBIQ, r)
1472 opset(AVSBIQ, r)
1473 opset(AVMSLG, r)
1474 opset(AVMSLEG, r)
1475 opset(AVMSLOG, r)
1476 opset(AVMSLEOG, r)
1477 case AVSEL:
1478 opset(AVFMADB, r)
1479 opset(AWFMADB, r)
1480 opset(AVFMSDB, r)
1481 opset(AWFMSDB, r)
1482 opset(AVPERM, r)
1483 case AKM:
1484 opset(AKMC, r)
1485 opset(AKLMD, r)
1486 opset(AKIMD, r)
1487 case AKMA:
1488 opset(AKMCTR, r)
1489 }
1490 }
1491 }
1492
1493 const (
1494 op_A uint32 = 0x5A00
1495 op_AD uint32 = 0x6A00
1496 op_ADB uint32 = 0xED1A
1497 op_ADBR uint32 = 0xB31A
1498 op_ADR uint32 = 0x2A00
1499 op_ADTR uint32 = 0xB3D2
1500 op_ADTRA uint32 = 0xB3D2
1501 op_AE uint32 = 0x7A00
1502 op_AEB uint32 = 0xED0A
1503 op_AEBR uint32 = 0xB30A
1504 op_AER uint32 = 0x3A00
1505 op_AFI uint32 = 0xC209
1506 op_AG uint32 = 0xE308
1507 op_AGF uint32 = 0xE318
1508 op_AGFI uint32 = 0xC208
1509 op_AGFR uint32 = 0xB918
1510 op_AGHI uint32 = 0xA70B
1511 op_AGHIK uint32 = 0xECD9
1512 op_AGR uint32 = 0xB908
1513 op_AGRK uint32 = 0xB9E8
1514 op_AGSI uint32 = 0xEB7A
1515 op_AH uint32 = 0x4A00
1516 op_AHHHR uint32 = 0xB9C8
1517 op_AHHLR uint32 = 0xB9D8
1518 op_AHI uint32 = 0xA70A
1519 op_AHIK uint32 = 0xECD8
1520 op_AHY uint32 = 0xE37A
1521 op_AIH uint32 = 0xCC08
1522 op_AL uint32 = 0x5E00
1523 op_ALC uint32 = 0xE398
1524 op_ALCG uint32 = 0xE388
1525 op_ALCGR uint32 = 0xB988
1526 op_ALCR uint32 = 0xB998
1527 op_ALFI uint32 = 0xC20B
1528 op_ALG uint32 = 0xE30A
1529 op_ALGF uint32 = 0xE31A
1530 op_ALGFI uint32 = 0xC20A
1531 op_ALGFR uint32 = 0xB91A
1532 op_ALGHSIK uint32 = 0xECDB
1533 op_ALGR uint32 = 0xB90A
1534 op_ALGRK uint32 = 0xB9EA
1535 op_ALGSI uint32 = 0xEB7E
1536 op_ALHHHR uint32 = 0xB9CA
1537 op_ALHHLR uint32 = 0xB9DA
1538 op_ALHSIK uint32 = 0xECDA
1539 op_ALR uint32 = 0x1E00
1540 op_ALRK uint32 = 0xB9FA
1541 op_ALSI uint32 = 0xEB6E
1542 op_ALSIH uint32 = 0xCC0A
1543 op_ALSIHN uint32 = 0xCC0B
1544 op_ALY uint32 = 0xE35E
1545 op_AP uint32 = 0xFA00
1546 op_AR uint32 = 0x1A00
1547 op_ARK uint32 = 0xB9F8
1548 op_ASI uint32 = 0xEB6A
1549 op_AU uint32 = 0x7E00
1550 op_AUR uint32 = 0x3E00
1551 op_AW uint32 = 0x6E00
1552 op_AWR uint32 = 0x2E00
1553 op_AXBR uint32 = 0xB34A
1554 op_AXR uint32 = 0x3600
1555 op_AXTR uint32 = 0xB3DA
1556 op_AXTRA uint32 = 0xB3DA
1557 op_AY uint32 = 0xE35A
1558 op_BAKR uint32 = 0xB240
1559 op_BAL uint32 = 0x4500
1560 op_BALR uint32 = 0x0500
1561 op_BAS uint32 = 0x4D00
1562 op_BASR uint32 = 0x0D00
1563 op_BASSM uint32 = 0x0C00
1564 op_BC uint32 = 0x4700
1565 op_BCR uint32 = 0x0700
1566 op_BCT uint32 = 0x4600
1567 op_BCTG uint32 = 0xE346
1568 op_BCTGR uint32 = 0xB946
1569 op_BCTR uint32 = 0x0600
1570 op_BPP uint32 = 0xC700
1571 op_BPRP uint32 = 0xC500
1572 op_BRAS uint32 = 0xA705
1573 op_BRASL uint32 = 0xC005
1574 op_BRC uint32 = 0xA704
1575 op_BRCL uint32 = 0xC004
1576 op_BRCT uint32 = 0xA706
1577 op_BRCTG uint32 = 0xA707
1578 op_BRCTH uint32 = 0xCC06
1579 op_BRXH uint32 = 0x8400
1580 op_BRXHG uint32 = 0xEC44
1581 op_BRXLE uint32 = 0x8500
1582 op_BRXLG uint32 = 0xEC45
1583 op_BSA uint32 = 0xB25A
1584 op_BSG uint32 = 0xB258
1585 op_BSM uint32 = 0x0B00
1586 op_BXH uint32 = 0x8600
1587 op_BXHG uint32 = 0xEB44
1588 op_BXLE uint32 = 0x8700
1589 op_BXLEG uint32 = 0xEB45
1590 op_C uint32 = 0x5900
1591 op_CD uint32 = 0x6900
1592 op_CDB uint32 = 0xED19
1593 op_CDBR uint32 = 0xB319
1594 op_CDFBR uint32 = 0xB395
1595 op_CDFBRA uint32 = 0xB395
1596 op_CDFR uint32 = 0xB3B5
1597 op_CDFTR uint32 = 0xB951
1598 op_CDGBR uint32 = 0xB3A5
1599 op_CDGBRA uint32 = 0xB3A5
1600 op_CDGR uint32 = 0xB3C5
1601 op_CDGTR uint32 = 0xB3F1
1602 op_CDGTRA uint32 = 0xB3F1
1603 op_CDLFBR uint32 = 0xB391
1604 op_CDLFTR uint32 = 0xB953
1605 op_CDLGBR uint32 = 0xB3A1
1606 op_CDLGTR uint32 = 0xB952
1607 op_CDR uint32 = 0x2900
1608 op_CDS uint32 = 0xBB00
1609 op_CDSG uint32 = 0xEB3E
1610 op_CDSTR uint32 = 0xB3F3
1611 op_CDSY uint32 = 0xEB31
1612 op_CDTR uint32 = 0xB3E4
1613 op_CDUTR uint32 = 0xB3F2
1614 op_CDZT uint32 = 0xEDAA
1615 op_CE uint32 = 0x7900
1616 op_CEB uint32 = 0xED09
1617 op_CEBR uint32 = 0xB309
1618 op_CEDTR uint32 = 0xB3F4
1619 op_CEFBR uint32 = 0xB394
1620 op_CEFBRA uint32 = 0xB394
1621 op_CEFR uint32 = 0xB3B4
1622 op_CEGBR uint32 = 0xB3A4
1623 op_CEGBRA uint32 = 0xB3A4
1624 op_CEGR uint32 = 0xB3C4
1625 op_CELFBR uint32 = 0xB390
1626 op_CELGBR uint32 = 0xB3A0
1627 op_CER uint32 = 0x3900
1628 op_CEXTR uint32 = 0xB3FC
1629 op_CFC uint32 = 0xB21A
1630 op_CFDBR uint32 = 0xB399
1631 op_CFDBRA uint32 = 0xB399
1632 op_CFDR uint32 = 0xB3B9
1633 op_CFDTR uint32 = 0xB941
1634 op_CFEBR uint32 = 0xB398
1635 op_CFEBRA uint32 = 0xB398
1636 op_CFER uint32 = 0xB3B8
1637 op_CFI uint32 = 0xC20D
1638 op_CFXBR uint32 = 0xB39A
1639 op_CFXBRA uint32 = 0xB39A
1640 op_CFXR uint32 = 0xB3BA
1641 op_CFXTR uint32 = 0xB949
1642 op_CG uint32 = 0xE320
1643 op_CGDBR uint32 = 0xB3A9
1644 op_CGDBRA uint32 = 0xB3A9
1645 op_CGDR uint32 = 0xB3C9
1646 op_CGDTR uint32 = 0xB3E1
1647 op_CGDTRA uint32 = 0xB3E1
1648 op_CGEBR uint32 = 0xB3A8
1649 op_CGEBRA uint32 = 0xB3A8
1650 op_CGER uint32 = 0xB3C8
1651 op_CGF uint32 = 0xE330
1652 op_CGFI uint32 = 0xC20C
1653 op_CGFR uint32 = 0xB930
1654 op_CGFRL uint32 = 0xC60C
1655 op_CGH uint32 = 0xE334
1656 op_CGHI uint32 = 0xA70F
1657 op_CGHRL uint32 = 0xC604
1658 op_CGHSI uint32 = 0xE558
1659 op_CGIB uint32 = 0xECFC
1660 op_CGIJ uint32 = 0xEC7C
1661 op_CGIT uint32 = 0xEC70
1662 op_CGR uint32 = 0xB920
1663 op_CGRB uint32 = 0xECE4
1664 op_CGRJ uint32 = 0xEC64
1665 op_CGRL uint32 = 0xC608
1666 op_CGRT uint32 = 0xB960
1667 op_CGXBR uint32 = 0xB3AA
1668 op_CGXBRA uint32 = 0xB3AA
1669 op_CGXR uint32 = 0xB3CA
1670 op_CGXTR uint32 = 0xB3E9
1671 op_CGXTRA uint32 = 0xB3E9
1672 op_CH uint32 = 0x4900
1673 op_CHF uint32 = 0xE3CD
1674 op_CHHR uint32 = 0xB9CD
1675 op_CHHSI uint32 = 0xE554
1676 op_CHI uint32 = 0xA70E
1677 op_CHLR uint32 = 0xB9DD
1678 op_CHRL uint32 = 0xC605
1679 op_CHSI uint32 = 0xE55C
1680 op_CHY uint32 = 0xE379
1681 op_CIB uint32 = 0xECFE
1682 op_CIH uint32 = 0xCC0D
1683 op_CIJ uint32 = 0xEC7E
1684 op_CIT uint32 = 0xEC72
1685 op_CKSM uint32 = 0xB241
1686 op_CL uint32 = 0x5500
1687 op_CLC uint32 = 0xD500
1688 op_CLCL uint32 = 0x0F00
1689 op_CLCLE uint32 = 0xA900
1690 op_CLCLU uint32 = 0xEB8F
1691 op_CLFDBR uint32 = 0xB39D
1692 op_CLFDTR uint32 = 0xB943
1693 op_CLFEBR uint32 = 0xB39C
1694 op_CLFHSI uint32 = 0xE55D
1695 op_CLFI uint32 = 0xC20F
1696 op_CLFIT uint32 = 0xEC73
1697 op_CLFXBR uint32 = 0xB39E
1698 op_CLFXTR uint32 = 0xB94B
1699 op_CLG uint32 = 0xE321
1700 op_CLGDBR uint32 = 0xB3AD
1701 op_CLGDTR uint32 = 0xB942
1702 op_CLGEBR uint32 = 0xB3AC
1703 op_CLGF uint32 = 0xE331
1704 op_CLGFI uint32 = 0xC20E
1705 op_CLGFR uint32 = 0xB931
1706 op_CLGFRL uint32 = 0xC60E
1707 op_CLGHRL uint32 = 0xC606
1708 op_CLGHSI uint32 = 0xE559
1709 op_CLGIB uint32 = 0xECFD
1710 op_CLGIJ uint32 = 0xEC7D
1711 op_CLGIT uint32 = 0xEC71
1712 op_CLGR uint32 = 0xB921
1713 op_CLGRB uint32 = 0xECE5
1714 op_CLGRJ uint32 = 0xEC65
1715 op_CLGRL uint32 = 0xC60A
1716 op_CLGRT uint32 = 0xB961
1717 op_CLGT uint32 = 0xEB2B
1718 op_CLGXBR uint32 = 0xB3AE
1719 op_CLGXTR uint32 = 0xB94A
1720 op_CLHF uint32 = 0xE3CF
1721 op_CLHHR uint32 = 0xB9CF
1722 op_CLHHSI uint32 = 0xE555
1723 op_CLHLR uint32 = 0xB9DF
1724 op_CLHRL uint32 = 0xC607
1725 op_CLI uint32 = 0x9500
1726 op_CLIB uint32 = 0xECFF
1727 op_CLIH uint32 = 0xCC0F
1728 op_CLIJ uint32 = 0xEC7F
1729 op_CLIY uint32 = 0xEB55
1730 op_CLM uint32 = 0xBD00
1731 op_CLMH uint32 = 0xEB20
1732 op_CLMY uint32 = 0xEB21
1733 op_CLR uint32 = 0x1500
1734 op_CLRB uint32 = 0xECF7
1735 op_CLRJ uint32 = 0xEC77
1736 op_CLRL uint32 = 0xC60F
1737 op_CLRT uint32 = 0xB973
1738 op_CLST uint32 = 0xB25D
1739 op_CLT uint32 = 0xEB23
1740 op_CLY uint32 = 0xE355
1741 op_CMPSC uint32 = 0xB263
1742 op_CP uint32 = 0xF900
1743 op_CPSDR uint32 = 0xB372
1744 op_CPYA uint32 = 0xB24D
1745 op_CR uint32 = 0x1900
1746 op_CRB uint32 = 0xECF6
1747 op_CRDTE uint32 = 0xB98F
1748 op_CRJ uint32 = 0xEC76
1749 op_CRL uint32 = 0xC60D
1750 op_CRT uint32 = 0xB972
1751 op_CS uint32 = 0xBA00
1752 op_CSCH uint32 = 0xB230
1753 op_CSDTR uint32 = 0xB3E3
1754 op_CSG uint32 = 0xEB30
1755 op_CSP uint32 = 0xB250
1756 op_CSPG uint32 = 0xB98A
1757 op_CSST uint32 = 0xC802
1758 op_CSXTR uint32 = 0xB3EB
1759 op_CSY uint32 = 0xEB14
1760 op_CU12 uint32 = 0xB2A7
1761 op_CU14 uint32 = 0xB9B0
1762 op_CU21 uint32 = 0xB2A6
1763 op_CU24 uint32 = 0xB9B1
1764 op_CU41 uint32 = 0xB9B2
1765 op_CU42 uint32 = 0xB9B3
1766 op_CUDTR uint32 = 0xB3E2
1767 op_CUSE uint32 = 0xB257
1768 op_CUTFU uint32 = 0xB2A7
1769 op_CUUTF uint32 = 0xB2A6
1770 op_CUXTR uint32 = 0xB3EA
1771 op_CVB uint32 = 0x4F00
1772 op_CVBG uint32 = 0xE30E
1773 op_CVBY uint32 = 0xE306
1774 op_CVD uint32 = 0x4E00
1775 op_CVDG uint32 = 0xE32E
1776 op_CVDY uint32 = 0xE326
1777 op_CXBR uint32 = 0xB349
1778 op_CXFBR uint32 = 0xB396
1779 op_CXFBRA uint32 = 0xB396
1780 op_CXFR uint32 = 0xB3B6
1781 op_CXFTR uint32 = 0xB959
1782 op_CXGBR uint32 = 0xB3A6
1783 op_CXGBRA uint32 = 0xB3A6
1784 op_CXGR uint32 = 0xB3C6
1785 op_CXGTR uint32 = 0xB3F9
1786 op_CXGTRA uint32 = 0xB3F9
1787 op_CXLFBR uint32 = 0xB392
1788 op_CXLFTR uint32 = 0xB95B
1789 op_CXLGBR uint32 = 0xB3A2
1790 op_CXLGTR uint32 = 0xB95A
1791 op_CXR uint32 = 0xB369
1792 op_CXSTR uint32 = 0xB3FB
1793 op_CXTR uint32 = 0xB3EC
1794 op_CXUTR uint32 = 0xB3FA
1795 op_CXZT uint32 = 0xEDAB
1796 op_CY uint32 = 0xE359
1797 op_CZDT uint32 = 0xEDA8
1798 op_CZXT uint32 = 0xEDA9
1799 op_D uint32 = 0x5D00
1800 op_DD uint32 = 0x6D00
1801 op_DDB uint32 = 0xED1D
1802 op_DDBR uint32 = 0xB31D
1803 op_DDR uint32 = 0x2D00
1804 op_DDTR uint32 = 0xB3D1
1805 op_DDTRA uint32 = 0xB3D1
1806 op_DE uint32 = 0x7D00
1807 op_DEB uint32 = 0xED0D
1808 op_DEBR uint32 = 0xB30D
1809 op_DER uint32 = 0x3D00
1810 op_DIDBR uint32 = 0xB35B
1811 op_DIEBR uint32 = 0xB353
1812 op_DL uint32 = 0xE397
1813 op_DLG uint32 = 0xE387
1814 op_DLGR uint32 = 0xB987
1815 op_DLR uint32 = 0xB997
1816 op_DP uint32 = 0xFD00
1817 op_DR uint32 = 0x1D00
1818 op_DSG uint32 = 0xE30D
1819 op_DSGF uint32 = 0xE31D
1820 op_DSGFR uint32 = 0xB91D
1821 op_DSGR uint32 = 0xB90D
1822 op_DXBR uint32 = 0xB34D
1823 op_DXR uint32 = 0xB22D
1824 op_DXTR uint32 = 0xB3D9
1825 op_DXTRA uint32 = 0xB3D9
1826 op_EAR uint32 = 0xB24F
1827 op_ECAG uint32 = 0xEB4C
1828 op_ECTG uint32 = 0xC801
1829 op_ED uint32 = 0xDE00
1830 op_EDMK uint32 = 0xDF00
1831 op_EEDTR uint32 = 0xB3E5
1832 op_EEXTR uint32 = 0xB3ED
1833 op_EFPC uint32 = 0xB38C
1834 op_EPAIR uint32 = 0xB99A
1835 op_EPAR uint32 = 0xB226
1836 op_EPSW uint32 = 0xB98D
1837 op_EREG uint32 = 0xB249
1838 op_EREGG uint32 = 0xB90E
1839 op_ESAIR uint32 = 0xB99B
1840 op_ESAR uint32 = 0xB227
1841 op_ESDTR uint32 = 0xB3E7
1842 op_ESEA uint32 = 0xB99D
1843 op_ESTA uint32 = 0xB24A
1844 op_ESXTR uint32 = 0xB3EF
1845 op_ETND uint32 = 0xB2EC
1846 op_EX uint32 = 0x4400
1847 op_EXRL uint32 = 0xC600
1848 op_FIDBR uint32 = 0xB35F
1849 op_FIDBRA uint32 = 0xB35F
1850 op_FIDR uint32 = 0xB37F
1851 op_FIDTR uint32 = 0xB3D7
1852 op_FIEBR uint32 = 0xB357
1853 op_FIEBRA uint32 = 0xB357
1854 op_FIER uint32 = 0xB377
1855 op_FIXBR uint32 = 0xB347
1856 op_FIXBRA uint32 = 0xB347
1857 op_FIXR uint32 = 0xB367
1858 op_FIXTR uint32 = 0xB3DF
1859 op_FLOGR uint32 = 0xB983
1860 op_HDR uint32 = 0x2400
1861 op_HER uint32 = 0x3400
1862 op_HSCH uint32 = 0xB231
1863 op_IAC uint32 = 0xB224
1864 op_IC uint32 = 0x4300
1865 op_ICM uint32 = 0xBF00
1866 op_ICMH uint32 = 0xEB80
1867 op_ICMY uint32 = 0xEB81
1868 op_ICY uint32 = 0xE373
1869 op_IDTE uint32 = 0xB98E
1870 op_IEDTR uint32 = 0xB3F6
1871 op_IEXTR uint32 = 0xB3FE
1872 op_IIHF uint32 = 0xC008
1873 op_IIHH uint32 = 0xA500
1874 op_IIHL uint32 = 0xA501
1875 op_IILF uint32 = 0xC009
1876 op_IILH uint32 = 0xA502
1877 op_IILL uint32 = 0xA503
1878 op_IPK uint32 = 0xB20B
1879 op_IPM uint32 = 0xB222
1880 op_IPTE uint32 = 0xB221
1881 op_ISKE uint32 = 0xB229
1882 op_IVSK uint32 = 0xB223
1883 op_KDB uint32 = 0xED18
1884 op_KDBR uint32 = 0xB318
1885 op_KDTR uint32 = 0xB3E0
1886 op_KEB uint32 = 0xED08
1887 op_KEBR uint32 = 0xB308
1888 op_KIMD uint32 = 0xB93E
1889 op_KLMD uint32 = 0xB93F
1890 op_KM uint32 = 0xB92E
1891 op_KMAC uint32 = 0xB91E
1892 op_KMC uint32 = 0xB92F
1893 op_KMA uint32 = 0xB929
1894 op_KMCTR uint32 = 0xB92D
1895 op_KMF uint32 = 0xB92A
1896 op_KMO uint32 = 0xB92B
1897 op_KXBR uint32 = 0xB348
1898 op_KXTR uint32 = 0xB3E8
1899 op_L uint32 = 0x5800
1900 op_LA uint32 = 0x4100
1901 op_LAA uint32 = 0xEBF8
1902 op_LAAG uint32 = 0xEBE8
1903 op_LAAL uint32 = 0xEBFA
1904 op_LAALG uint32 = 0xEBEA
1905 op_LAE uint32 = 0x5100
1906 op_LAEY uint32 = 0xE375
1907 op_LAM uint32 = 0x9A00
1908 op_LAMY uint32 = 0xEB9A
1909 op_LAN uint32 = 0xEBF4
1910 op_LANG uint32 = 0xEBE4
1911 op_LAO uint32 = 0xEBF6
1912 op_LAOG uint32 = 0xEBE6
1913 op_LARL uint32 = 0xC000
1914 op_LASP uint32 = 0xE500
1915 op_LAT uint32 = 0xE39F
1916 op_LAX uint32 = 0xEBF7
1917 op_LAXG uint32 = 0xEBE7
1918 op_LAY uint32 = 0xE371
1919 op_LB uint32 = 0xE376
1920 op_LBH uint32 = 0xE3C0
1921 op_LBR uint32 = 0xB926
1922 op_LCDBR uint32 = 0xB313
1923 op_LCDFR uint32 = 0xB373
1924 op_LCDR uint32 = 0x2300
1925 op_LCEBR uint32 = 0xB303
1926 op_LCER uint32 = 0x3300
1927 op_LCGFR uint32 = 0xB913
1928 op_LCGR uint32 = 0xB903
1929 op_LCR uint32 = 0x1300
1930 op_LCTL uint32 = 0xB700
1931 op_LCTLG uint32 = 0xEB2F
1932 op_LCXBR uint32 = 0xB343
1933 op_LCXR uint32 = 0xB363
1934 op_LD uint32 = 0x6800
1935 op_LDE uint32 = 0xED24
1936 op_LDEB uint32 = 0xED04
1937 op_LDEBR uint32 = 0xB304
1938 op_LDER uint32 = 0xB324
1939 op_LDETR uint32 = 0xB3D4
1940 op_LDGR uint32 = 0xB3C1
1941 op_LDR uint32 = 0x2800
1942 op_LDXBR uint32 = 0xB345
1943 op_LDXBRA uint32 = 0xB345
1944 op_LDXR uint32 = 0x2500
1945 op_LDXTR uint32 = 0xB3DD
1946 op_LDY uint32 = 0xED65
1947 op_LE uint32 = 0x7800
1948 op_LEDBR uint32 = 0xB344
1949 op_LEDBRA uint32 = 0xB344
1950 op_LEDR uint32 = 0x3500
1951 op_LEDTR uint32 = 0xB3D5
1952 op_LER uint32 = 0x3800
1953 op_LEXBR uint32 = 0xB346
1954 op_LEXBRA uint32 = 0xB346
1955 op_LEXR uint32 = 0xB366
1956 op_LEY uint32 = 0xED64
1957 op_LFAS uint32 = 0xB2BD
1958 op_LFH uint32 = 0xE3CA
1959 op_LFHAT uint32 = 0xE3C8
1960 op_LFPC uint32 = 0xB29D
1961 op_LG uint32 = 0xE304
1962 op_LGAT uint32 = 0xE385
1963 op_LGB uint32 = 0xE377
1964 op_LGBR uint32 = 0xB906
1965 op_LGDR uint32 = 0xB3CD
1966 op_LGF uint32 = 0xE314
1967 op_LGFI uint32 = 0xC001
1968 op_LGFR uint32 = 0xB914
1969 op_LGFRL uint32 = 0xC40C
1970 op_LGH uint32 = 0xE315
1971 op_LGHI uint32 = 0xA709
1972 op_LGHR uint32 = 0xB907
1973 op_LGHRL uint32 = 0xC404
1974 op_LGR uint32 = 0xB904
1975 op_LGRL uint32 = 0xC408
1976 op_LH uint32 = 0x4800
1977 op_LHH uint32 = 0xE3C4
1978 op_LHI uint32 = 0xA708
1979 op_LHR uint32 = 0xB927
1980 op_LHRL uint32 = 0xC405
1981 op_LHY uint32 = 0xE378
1982 op_LLC uint32 = 0xE394
1983 op_LLCH uint32 = 0xE3C2
1984 op_LLCR uint32 = 0xB994
1985 op_LLGC uint32 = 0xE390
1986 op_LLGCR uint32 = 0xB984
1987 op_LLGF uint32 = 0xE316
1988 op_LLGFAT uint32 = 0xE39D
1989 op_LLGFR uint32 = 0xB916
1990 op_LLGFRL uint32 = 0xC40E
1991 op_LLGH uint32 = 0xE391
1992 op_LLGHR uint32 = 0xB985
1993 op_LLGHRL uint32 = 0xC406
1994 op_LLGT uint32 = 0xE317
1995 op_LLGTAT uint32 = 0xE39C
1996 op_LLGTR uint32 = 0xB917
1997 op_LLH uint32 = 0xE395
1998 op_LLHH uint32 = 0xE3C6
1999 op_LLHR uint32 = 0xB995
2000 op_LLHRL uint32 = 0xC402
2001 op_LLIHF uint32 = 0xC00E
2002 op_LLIHH uint32 = 0xA50C
2003 op_LLIHL uint32 = 0xA50D
2004 op_LLILF uint32 = 0xC00F
2005 op_LLILH uint32 = 0xA50E
2006 op_LLILL uint32 = 0xA50F
2007 op_LM uint32 = 0x9800
2008 op_LMD uint32 = 0xEF00
2009 op_LMG uint32 = 0xEB04
2010 op_LMH uint32 = 0xEB96
2011 op_LMY uint32 = 0xEB98
2012 op_LNDBR uint32 = 0xB311
2013 op_LNDFR uint32 = 0xB371
2014 op_LNDR uint32 = 0x2100
2015 op_LNEBR uint32 = 0xB301
2016 op_LNER uint32 = 0x3100
2017 op_LNGFR uint32 = 0xB911
2018 op_LNGR uint32 = 0xB901
2019 op_LNR uint32 = 0x1100
2020 op_LNXBR uint32 = 0xB341
2021 op_LNXR uint32 = 0xB361
2022 op_LOC uint32 = 0xEBF2
2023 op_LOCG uint32 = 0xEBE2
2024 op_LOCGR uint32 = 0xB9E2
2025 op_LOCR uint32 = 0xB9F2
2026 op_LPD uint32 = 0xC804
2027 op_LPDBR uint32 = 0xB310
2028 op_LPDFR uint32 = 0xB370
2029 op_LPDG uint32 = 0xC805
2030 op_LPDR uint32 = 0x2000
2031 op_LPEBR uint32 = 0xB300
2032 op_LPER uint32 = 0x3000
2033 op_LPGFR uint32 = 0xB910
2034 op_LPGR uint32 = 0xB900
2035 op_LPQ uint32 = 0xE38F
2036 op_LPR uint32 = 0x1000
2037 op_LPSW uint32 = 0x8200
2038 op_LPSWE uint32 = 0xB2B2
2039 op_LPTEA uint32 = 0xB9AA
2040 op_LPXBR uint32 = 0xB340
2041 op_LPXR uint32 = 0xB360
2042 op_LR uint32 = 0x1800
2043 op_LRA uint32 = 0xB100
2044 op_LRAG uint32 = 0xE303
2045 op_LRAY uint32 = 0xE313
2046 op_LRDR uint32 = 0x2500
2047 op_LRER uint32 = 0x3500
2048 op_LRL uint32 = 0xC40D
2049 op_LRV uint32 = 0xE31E
2050 op_LRVG uint32 = 0xE30F
2051 op_LRVGR uint32 = 0xB90F
2052 op_LRVH uint32 = 0xE31F
2053 op_LRVR uint32 = 0xB91F
2054 op_LT uint32 = 0xE312
2055 op_LTDBR uint32 = 0xB312
2056 op_LTDR uint32 = 0x2200
2057 op_LTDTR uint32 = 0xB3D6
2058 op_LTEBR uint32 = 0xB302
2059 op_LTER uint32 = 0x3200
2060 op_LTG uint32 = 0xE302
2061 op_LTGF uint32 = 0xE332
2062 op_LTGFR uint32 = 0xB912
2063 op_LTGR uint32 = 0xB902
2064 op_LTR uint32 = 0x1200
2065 op_LTXBR uint32 = 0xB342
2066 op_LTXR uint32 = 0xB362
2067 op_LTXTR uint32 = 0xB3DE
2068 op_LURA uint32 = 0xB24B
2069 op_LURAG uint32 = 0xB905
2070 op_LXD uint32 = 0xED25
2071 op_LXDB uint32 = 0xED05
2072 op_LXDBR uint32 = 0xB305
2073 op_LXDR uint32 = 0xB325
2074 op_LXDTR uint32 = 0xB3DC
2075 op_LXE uint32 = 0xED26
2076 op_LXEB uint32 = 0xED06
2077 op_LXEBR uint32 = 0xB306
2078 op_LXER uint32 = 0xB326
2079 op_LXR uint32 = 0xB365
2080 op_LY uint32 = 0xE358
2081 op_LZDR uint32 = 0xB375
2082 op_LZER uint32 = 0xB374
2083 op_LZXR uint32 = 0xB376
2084 op_M uint32 = 0x5C00
2085 op_MAD uint32 = 0xED3E
2086 op_MADB uint32 = 0xED1E
2087 op_MADBR uint32 = 0xB31E
2088 op_MADR uint32 = 0xB33E
2089 op_MAE uint32 = 0xED2E
2090 op_MAEB uint32 = 0xED0E
2091 op_MAEBR uint32 = 0xB30E
2092 op_MAER uint32 = 0xB32E
2093 op_MAY uint32 = 0xED3A
2094 op_MAYH uint32 = 0xED3C
2095 op_MAYHR uint32 = 0xB33C
2096 op_MAYL uint32 = 0xED38
2097 op_MAYLR uint32 = 0xB338
2098 op_MAYR uint32 = 0xB33A
2099 op_MC uint32 = 0xAF00
2100 op_MD uint32 = 0x6C00
2101 op_MDB uint32 = 0xED1C
2102 op_MDBR uint32 = 0xB31C
2103 op_MDE uint32 = 0x7C00
2104 op_MDEB uint32 = 0xED0C
2105 op_MDEBR uint32 = 0xB30C
2106 op_MDER uint32 = 0x3C00
2107 op_MDR uint32 = 0x2C00
2108 op_MDTR uint32 = 0xB3D0
2109 op_MDTRA uint32 = 0xB3D0
2110 op_ME uint32 = 0x7C00
2111 op_MEE uint32 = 0xED37
2112 op_MEEB uint32 = 0xED17
2113 op_MEEBR uint32 = 0xB317
2114 op_MEER uint32 = 0xB337
2115 op_MER uint32 = 0x3C00
2116 op_MFY uint32 = 0xE35C
2117 op_MGHI uint32 = 0xA70D
2118 op_MH uint32 = 0x4C00
2119 op_MHI uint32 = 0xA70C
2120 op_MHY uint32 = 0xE37C
2121 op_ML uint32 = 0xE396
2122 op_MLG uint32 = 0xE386
2123 op_MLGR uint32 = 0xB986
2124 op_MLR uint32 = 0xB996
2125 op_MP uint32 = 0xFC00
2126 op_MR uint32 = 0x1C00
2127 op_MS uint32 = 0x7100
2128 op_MSCH uint32 = 0xB232
2129 op_MSD uint32 = 0xED3F
2130 op_MSDB uint32 = 0xED1F
2131 op_MSDBR uint32 = 0xB31F
2132 op_MSDR uint32 = 0xB33F
2133 op_MSE uint32 = 0xED2F
2134 op_MSEB uint32 = 0xED0F
2135 op_MSEBR uint32 = 0xB30F
2136 op_MSER uint32 = 0xB32F
2137 op_MSFI uint32 = 0xC201
2138 op_MSG uint32 = 0xE30C
2139 op_MSGF uint32 = 0xE31C
2140 op_MSGFI uint32 = 0xC200
2141 op_MSGFR uint32 = 0xB91C
2142 op_MSGR uint32 = 0xB90C
2143 op_MSR uint32 = 0xB252
2144 op_MSTA uint32 = 0xB247
2145 op_MSY uint32 = 0xE351
2146 op_MVC uint32 = 0xD200
2147 op_MVCDK uint32 = 0xE50F
2148 op_MVCIN uint32 = 0xE800
2149 op_MVCK uint32 = 0xD900
2150 op_MVCL uint32 = 0x0E00
2151 op_MVCLE uint32 = 0xA800
2152 op_MVCLU uint32 = 0xEB8E
2153 op_MVCOS uint32 = 0xC800
2154 op_MVCP uint32 = 0xDA00
2155 op_MVCS uint32 = 0xDB00
2156 op_MVCSK uint32 = 0xE50E
2157 op_MVGHI uint32 = 0xE548
2158 op_MVHHI uint32 = 0xE544
2159 op_MVHI uint32 = 0xE54C
2160 op_MVI uint32 = 0x9200
2161 op_MVIY uint32 = 0xEB52
2162 op_MVN uint32 = 0xD100
2163 op_MVO uint32 = 0xF100
2164 op_MVPG uint32 = 0xB254
2165 op_MVST uint32 = 0xB255
2166 op_MVZ uint32 = 0xD300
2167 op_MXBR uint32 = 0xB34C
2168 op_MXD uint32 = 0x6700
2169 op_MXDB uint32 = 0xED07
2170 op_MXDBR uint32 = 0xB307
2171 op_MXDR uint32 = 0x2700
2172 op_MXR uint32 = 0x2600
2173 op_MXTR uint32 = 0xB3D8
2174 op_MXTRA uint32 = 0xB3D8
2175 op_MY uint32 = 0xED3B
2176 op_MYH uint32 = 0xED3D
2177 op_MYHR uint32 = 0xB33D
2178 op_MYL uint32 = 0xED39
2179 op_MYLR uint32 = 0xB339
2180 op_MYR uint32 = 0xB33B
2181 op_N uint32 = 0x5400
2182 op_NC uint32 = 0xD400
2183 op_NG uint32 = 0xE380
2184 op_NGR uint32 = 0xB980
2185 op_NGRK uint32 = 0xB9E4
2186 op_NI uint32 = 0x9400
2187 op_NIAI uint32 = 0xB2FA
2188 op_NIHF uint32 = 0xC00A
2189 op_NIHH uint32 = 0xA504
2190 op_NIHL uint32 = 0xA505
2191 op_NILF uint32 = 0xC00B
2192 op_NILH uint32 = 0xA506
2193 op_NILL uint32 = 0xA507
2194 op_NIY uint32 = 0xEB54
2195 op_NR uint32 = 0x1400
2196 op_NRK uint32 = 0xB9F4
2197 op_NTSTG uint32 = 0xE325
2198 op_NY uint32 = 0xE354
2199 op_O uint32 = 0x5600
2200 op_OC uint32 = 0xD600
2201 op_OG uint32 = 0xE381
2202 op_OGR uint32 = 0xB981
2203 op_OGRK uint32 = 0xB9E6
2204 op_OI uint32 = 0x9600
2205 op_OIHF uint32 = 0xC00C
2206 op_OIHH uint32 = 0xA508
2207 op_OIHL uint32 = 0xA509
2208 op_OILF uint32 = 0xC00D
2209 op_OILH uint32 = 0xA50A
2210 op_OILL uint32 = 0xA50B
2211 op_OIY uint32 = 0xEB56
2212 op_OR uint32 = 0x1600
2213 op_ORK uint32 = 0xB9F6
2214 op_OY uint32 = 0xE356
2215 op_PACK uint32 = 0xF200
2216 op_PALB uint32 = 0xB248
2217 op_PC uint32 = 0xB218
2218 op_PCC uint32 = 0xB92C
2219 op_PCKMO uint32 = 0xB928
2220 op_PFD uint32 = 0xE336
2221 op_PFDRL uint32 = 0xC602
2222 op_PFMF uint32 = 0xB9AF
2223 op_PFPO uint32 = 0x010A
2224 op_PGIN uint32 = 0xB22E
2225 op_PGOUT uint32 = 0xB22F
2226 op_PKA uint32 = 0xE900
2227 op_PKU uint32 = 0xE100
2228 op_PLO uint32 = 0xEE00
2229 op_POPCNT uint32 = 0xB9E1
2230 op_PPA uint32 = 0xB2E8
2231 op_PR uint32 = 0x0101
2232 op_PT uint32 = 0xB228
2233 op_PTF uint32 = 0xB9A2
2234 op_PTFF uint32 = 0x0104
2235 op_PTI uint32 = 0xB99E
2236 op_PTLB uint32 = 0xB20D
2237 op_QADTR uint32 = 0xB3F5
2238 op_QAXTR uint32 = 0xB3FD
2239 op_RCHP uint32 = 0xB23B
2240 op_RISBG uint32 = 0xEC55
2241 op_RISBGN uint32 = 0xEC59
2242 op_RISBHG uint32 = 0xEC5D
2243 op_RISBLG uint32 = 0xEC51
2244 op_RLL uint32 = 0xEB1D
2245 op_RLLG uint32 = 0xEB1C
2246 op_RNSBG uint32 = 0xEC54
2247 op_ROSBG uint32 = 0xEC56
2248 op_RP uint32 = 0xB277
2249 op_RRBE uint32 = 0xB22A
2250 op_RRBM uint32 = 0xB9AE
2251 op_RRDTR uint32 = 0xB3F7
2252 op_RRXTR uint32 = 0xB3FF
2253 op_RSCH uint32 = 0xB238
2254 op_RXSBG uint32 = 0xEC57
2255 op_S uint32 = 0x5B00
2256 op_SAC uint32 = 0xB219
2257 op_SACF uint32 = 0xB279
2258 op_SAL uint32 = 0xB237
2259 op_SAM24 uint32 = 0x010C
2260 op_SAM31 uint32 = 0x010D
2261 op_SAM64 uint32 = 0x010E
2262 op_SAR uint32 = 0xB24E
2263 op_SCHM uint32 = 0xB23C
2264 op_SCK uint32 = 0xB204
2265 op_SCKC uint32 = 0xB206
2266 op_SCKPF uint32 = 0x0107
2267 op_SD uint32 = 0x6B00
2268 op_SDB uint32 = 0xED1B
2269 op_SDBR uint32 = 0xB31B
2270 op_SDR uint32 = 0x2B00
2271 op_SDTR uint32 = 0xB3D3
2272 op_SDTRA uint32 = 0xB3D3
2273 op_SE uint32 = 0x7B00
2274 op_SEB uint32 = 0xED0B
2275 op_SEBR uint32 = 0xB30B
2276 op_SER uint32 = 0x3B00
2277 op_SFASR uint32 = 0xB385
2278 op_SFPC uint32 = 0xB384
2279 op_SG uint32 = 0xE309
2280 op_SGF uint32 = 0xE319
2281 op_SGFR uint32 = 0xB919
2282 op_SGR uint32 = 0xB909
2283 op_SGRK uint32 = 0xB9E9
2284 op_SH uint32 = 0x4B00
2285 op_SHHHR uint32 = 0xB9C9
2286 op_SHHLR uint32 = 0xB9D9
2287 op_SHY uint32 = 0xE37B
2288 op_SIGP uint32 = 0xAE00
2289 op_SL uint32 = 0x5F00
2290 op_SLA uint32 = 0x8B00
2291 op_SLAG uint32 = 0xEB0B
2292 op_SLAK uint32 = 0xEBDD
2293 op_SLB uint32 = 0xE399
2294 op_SLBG uint32 = 0xE389
2295 op_SLBGR uint32 = 0xB989
2296 op_SLBR uint32 = 0xB999
2297 op_SLDA uint32 = 0x8F00
2298 op_SLDL uint32 = 0x8D00
2299 op_SLDT uint32 = 0xED40
2300 op_SLFI uint32 = 0xC205
2301 op_SLG uint32 = 0xE30B
2302 op_SLGF uint32 = 0xE31B
2303 op_SLGFI uint32 = 0xC204
2304 op_SLGFR uint32 = 0xB91B
2305 op_SLGR uint32 = 0xB90B
2306 op_SLGRK uint32 = 0xB9EB
2307 op_SLHHHR uint32 = 0xB9CB
2308 op_SLHHLR uint32 = 0xB9DB
2309 op_SLL uint32 = 0x8900
2310 op_SLLG uint32 = 0xEB0D
2311 op_SLLK uint32 = 0xEBDF
2312 op_SLR uint32 = 0x1F00
2313 op_SLRK uint32 = 0xB9FB
2314 op_SLXT uint32 = 0xED48
2315 op_SLY uint32 = 0xE35F
2316 op_SP uint32 = 0xFB00
2317 op_SPKA uint32 = 0xB20A
2318 op_SPM uint32 = 0x0400
2319 op_SPT uint32 = 0xB208
2320 op_SPX uint32 = 0xB210
2321 op_SQD uint32 = 0xED35
2322 op_SQDB uint32 = 0xED15
2323 op_SQDBR uint32 = 0xB315
2324 op_SQDR uint32 = 0xB244
2325 op_SQE uint32 = 0xED34
2326 op_SQEB uint32 = 0xED14
2327 op_SQEBR uint32 = 0xB314
2328 op_SQER uint32 = 0xB245
2329 op_SQXBR uint32 = 0xB316
2330 op_SQXR uint32 = 0xB336
2331 op_SR uint32 = 0x1B00
2332 op_SRA uint32 = 0x8A00
2333 op_SRAG uint32 = 0xEB0A
2334 op_SRAK uint32 = 0xEBDC
2335 op_SRDA uint32 = 0x8E00
2336 op_SRDL uint32 = 0x8C00
2337 op_SRDT uint32 = 0xED41
2338 op_SRK uint32 = 0xB9F9
2339 op_SRL uint32 = 0x8800
2340 op_SRLG uint32 = 0xEB0C
2341 op_SRLK uint32 = 0xEBDE
2342 op_SRNM uint32 = 0xB299
2343 op_SRNMB uint32 = 0xB2B8
2344 op_SRNMT uint32 = 0xB2B9
2345 op_SRP uint32 = 0xF000
2346 op_SRST uint32 = 0xB25E
2347 op_SRSTU uint32 = 0xB9BE
2348 op_SRXT uint32 = 0xED49
2349 op_SSAIR uint32 = 0xB99F
2350 op_SSAR uint32 = 0xB225
2351 op_SSCH uint32 = 0xB233
2352 op_SSKE uint32 = 0xB22B
2353 op_SSM uint32 = 0x8000
2354 op_ST uint32 = 0x5000
2355 op_STAM uint32 = 0x9B00
2356 op_STAMY uint32 = 0xEB9B
2357 op_STAP uint32 = 0xB212
2358 op_STC uint32 = 0x4200
2359 op_STCH uint32 = 0xE3C3
2360 op_STCK uint32 = 0xB205
2361 op_STCKC uint32 = 0xB207
2362 op_STCKE uint32 = 0xB278
2363 op_STCKF uint32 = 0xB27C
2364 op_STCM uint32 = 0xBE00
2365 op_STCMH uint32 = 0xEB2C
2366 op_STCMY uint32 = 0xEB2D
2367 op_STCPS uint32 = 0xB23A
2368 op_STCRW uint32 = 0xB239
2369 op_STCTG uint32 = 0xEB25
2370 op_STCTL uint32 = 0xB600
2371 op_STCY uint32 = 0xE372
2372 op_STD uint32 = 0x6000
2373 op_STDY uint32 = 0xED67
2374 op_STE uint32 = 0x7000
2375 op_STEY uint32 = 0xED66
2376 op_STFH uint32 = 0xE3CB
2377 op_STFL uint32 = 0xB2B1
2378 op_STFLE uint32 = 0xB2B0
2379 op_STFPC uint32 = 0xB29C
2380 op_STG uint32 = 0xE324
2381 op_STGRL uint32 = 0xC40B
2382 op_STH uint32 = 0x4000
2383 op_STHH uint32 = 0xE3C7
2384 op_STHRL uint32 = 0xC407
2385 op_STHY uint32 = 0xE370
2386 op_STIDP uint32 = 0xB202
2387 op_STM uint32 = 0x9000
2388 op_STMG uint32 = 0xEB24
2389 op_STMH uint32 = 0xEB26
2390 op_STMY uint32 = 0xEB90
2391 op_STNSM uint32 = 0xAC00
2392 op_STOC uint32 = 0xEBF3
2393 op_STOCG uint32 = 0xEBE3
2394 op_STOSM uint32 = 0xAD00
2395 op_STPQ uint32 = 0xE38E
2396 op_STPT uint32 = 0xB209
2397 op_STPX uint32 = 0xB211
2398 op_STRAG uint32 = 0xE502
2399 op_STRL uint32 = 0xC40F
2400 op_STRV uint32 = 0xE33E
2401 op_STRVG uint32 = 0xE32F
2402 op_STRVH uint32 = 0xE33F
2403 op_STSCH uint32 = 0xB234
2404 op_STSI uint32 = 0xB27D
2405 op_STURA uint32 = 0xB246
2406 op_STURG uint32 = 0xB925
2407 op_STY uint32 = 0xE350
2408 op_SU uint32 = 0x7F00
2409 op_SUR uint32 = 0x3F00
2410 op_SVC uint32 = 0x0A00
2411 op_SW uint32 = 0x6F00
2412 op_SWR uint32 = 0x2F00
2413 op_SXBR uint32 = 0xB34B
2414 op_SXR uint32 = 0x3700
2415 op_SXTR uint32 = 0xB3DB
2416 op_SXTRA uint32 = 0xB3DB
2417 op_SY uint32 = 0xE35B
2418 op_TABORT uint32 = 0xB2FC
2419 op_TAM uint32 = 0x010B
2420 op_TAR uint32 = 0xB24C
2421 op_TB uint32 = 0xB22C
2422 op_TBDR uint32 = 0xB351
2423 op_TBEDR uint32 = 0xB350
2424 op_TBEGIN uint32 = 0xE560
2425 op_TBEGINC uint32 = 0xE561
2426 op_TCDB uint32 = 0xED11
2427 op_TCEB uint32 = 0xED10
2428 op_TCXB uint32 = 0xED12
2429 op_TDCDT uint32 = 0xED54
2430 op_TDCET uint32 = 0xED50
2431 op_TDCXT uint32 = 0xED58
2432 op_TDGDT uint32 = 0xED55
2433 op_TDGET uint32 = 0xED51
2434 op_TDGXT uint32 = 0xED59
2435 op_TEND uint32 = 0xB2F8
2436 op_THDER uint32 = 0xB358
2437 op_THDR uint32 = 0xB359
2438 op_TM uint32 = 0x9100
2439 op_TMH uint32 = 0xA700
2440 op_TMHH uint32 = 0xA702
2441 op_TMHL uint32 = 0xA703
2442 op_TML uint32 = 0xA701
2443 op_TMLH uint32 = 0xA700
2444 op_TMLL uint32 = 0xA701
2445 op_TMY uint32 = 0xEB51
2446 op_TP uint32 = 0xEBC0
2447 op_TPI uint32 = 0xB236
2448 op_TPROT uint32 = 0xE501
2449 op_TR uint32 = 0xDC00
2450 op_TRACE uint32 = 0x9900
2451 op_TRACG uint32 = 0xEB0F
2452 op_TRAP2 uint32 = 0x01FF
2453 op_TRAP4 uint32 = 0xB2FF
2454 op_TRE uint32 = 0xB2A5
2455 op_TROO uint32 = 0xB993
2456 op_TROT uint32 = 0xB992
2457 op_TRT uint32 = 0xDD00
2458 op_TRTE uint32 = 0xB9BF
2459 op_TRTO uint32 = 0xB991
2460 op_TRTR uint32 = 0xD000
2461 op_TRTRE uint32 = 0xB9BD
2462 op_TRTT uint32 = 0xB990
2463 op_TS uint32 = 0x9300
2464 op_TSCH uint32 = 0xB235
2465 op_UNPK uint32 = 0xF300
2466 op_UNPKA uint32 = 0xEA00
2467 op_UNPKU uint32 = 0xE200
2468 op_UPT uint32 = 0x0102
2469 op_X uint32 = 0x5700
2470 op_XC uint32 = 0xD700
2471 op_XG uint32 = 0xE382
2472 op_XGR uint32 = 0xB982
2473 op_XGRK uint32 = 0xB9E7
2474 op_XI uint32 = 0x9700
2475 op_XIHF uint32 = 0xC006
2476 op_XILF uint32 = 0xC007
2477 op_XIY uint32 = 0xEB57
2478 op_XR uint32 = 0x1700
2479 op_XRK uint32 = 0xB9F7
2480 op_XSCH uint32 = 0xB276
2481 op_XY uint32 = 0xE357
2482 op_ZAP uint32 = 0xF800
2483 op_BRRK uint32 = 0x0001
2484
2485
2486 op_CXPT uint32 = 0xEDAF
2487 op_CDPT uint32 = 0xEDAE
2488 op_CPXT uint32 = 0xEDAD
2489 op_CPDT uint32 = 0xEDAC
2490 op_LZRF uint32 = 0xE33B
2491 op_LZRG uint32 = 0xE32A
2492 op_LCCB uint32 = 0xE727
2493 op_LOCHHI uint32 = 0xEC4E
2494 op_LOCHI uint32 = 0xEC42
2495 op_LOCGHI uint32 = 0xEC46
2496 op_LOCFH uint32 = 0xEBE0
2497 op_LOCFHR uint32 = 0xB9E0
2498 op_LLZRGF uint32 = 0xE33A
2499 op_STOCFH uint32 = 0xEBE1
2500 op_VA uint32 = 0xE7F3
2501 op_VACC uint32 = 0xE7F1
2502 op_VAC uint32 = 0xE7BB
2503 op_VACCC uint32 = 0xE7B9
2504 op_VN uint32 = 0xE768
2505 op_VNC uint32 = 0xE769
2506 op_VAVG uint32 = 0xE7F2
2507 op_VAVGL uint32 = 0xE7F0
2508 op_VCKSM uint32 = 0xE766
2509 op_VCEQ uint32 = 0xE7F8
2510 op_VCH uint32 = 0xE7FB
2511 op_VCHL uint32 = 0xE7F9
2512 op_VCLZ uint32 = 0xE753
2513 op_VCTZ uint32 = 0xE752
2514 op_VEC uint32 = 0xE7DB
2515 op_VECL uint32 = 0xE7D9
2516 op_VERIM uint32 = 0xE772
2517 op_VERLL uint32 = 0xE733
2518 op_VERLLV uint32 = 0xE773
2519 op_VESLV uint32 = 0xE770
2520 op_VESL uint32 = 0xE730
2521 op_VESRA uint32 = 0xE73A
2522 op_VESRAV uint32 = 0xE77A
2523 op_VESRL uint32 = 0xE738
2524 op_VESRLV uint32 = 0xE778
2525 op_VX uint32 = 0xE76D
2526 op_VFAE uint32 = 0xE782
2527 op_VFEE uint32 = 0xE780
2528 op_VFENE uint32 = 0xE781
2529 op_VFA uint32 = 0xE7E3
2530 op_WFK uint32 = 0xE7CA
2531 op_VFCE uint32 = 0xE7E8
2532 op_VFCH uint32 = 0xE7EB
2533 op_VFCHE uint32 = 0xE7EA
2534 op_WFC uint32 = 0xE7CB
2535 op_VCDG uint32 = 0xE7C3
2536 op_VCDLG uint32 = 0xE7C1
2537 op_VCGD uint32 = 0xE7C2
2538 op_VCLGD uint32 = 0xE7C0
2539 op_VFD uint32 = 0xE7E5
2540 op_VLDE uint32 = 0xE7C4
2541 op_VLED uint32 = 0xE7C5
2542 op_VFM uint32 = 0xE7E7
2543 op_VFMA uint32 = 0xE78F
2544 op_VFMS uint32 = 0xE78E
2545 op_VFPSO uint32 = 0xE7CC
2546 op_VFSQ uint32 = 0xE7CE
2547 op_VFS uint32 = 0xE7E2
2548 op_VFTCI uint32 = 0xE74A
2549 op_VGFM uint32 = 0xE7B4
2550 op_VGFMA uint32 = 0xE7BC
2551 op_VGEF uint32 = 0xE713
2552 op_VGEG uint32 = 0xE712
2553 op_VGBM uint32 = 0xE744
2554 op_VGM uint32 = 0xE746
2555 op_VISTR uint32 = 0xE75C
2556 op_VL uint32 = 0xE706
2557 op_VLR uint32 = 0xE756
2558 op_VLREP uint32 = 0xE705
2559 op_VLC uint32 = 0xE7DE
2560 op_VLEH uint32 = 0xE701
2561 op_VLEF uint32 = 0xE703
2562 op_VLEG uint32 = 0xE702
2563 op_VLEB uint32 = 0xE700
2564 op_VLEIH uint32 = 0xE741
2565 op_VLEIF uint32 = 0xE743
2566 op_VLEIG uint32 = 0xE742
2567 op_VLEIB uint32 = 0xE740
2568 op_VFI uint32 = 0xE7C7
2569 op_VLGV uint32 = 0xE721
2570 op_VLLEZ uint32 = 0xE704
2571 op_VLM uint32 = 0xE736
2572 op_VLP uint32 = 0xE7DF
2573 op_VLBB uint32 = 0xE707
2574 op_VLVG uint32 = 0xE722
2575 op_VLVGP uint32 = 0xE762
2576 op_VLL uint32 = 0xE737
2577 op_VMX uint32 = 0xE7FF
2578 op_VMXL uint32 = 0xE7FD
2579 op_VMRH uint32 = 0xE761
2580 op_VMRL uint32 = 0xE760
2581 op_VMN uint32 = 0xE7FE
2582 op_VMNL uint32 = 0xE7FC
2583 op_VMAE uint32 = 0xE7AE
2584 op_VMAH uint32 = 0xE7AB
2585 op_VMALE uint32 = 0xE7AC
2586 op_VMALH uint32 = 0xE7A9
2587 op_VMALO uint32 = 0xE7AD
2588 op_VMAL uint32 = 0xE7AA
2589 op_VMAO uint32 = 0xE7AF
2590 op_VME uint32 = 0xE7A6
2591 op_VMH uint32 = 0xE7A3
2592 op_VMLE uint32 = 0xE7A4
2593 op_VMLH uint32 = 0xE7A1
2594 op_VMLO uint32 = 0xE7A5
2595 op_VML uint32 = 0xE7A2
2596 op_VMO uint32 = 0xE7A7
2597 op_VNO uint32 = 0xE76B
2598 op_VO uint32 = 0xE76A
2599 op_VPK uint32 = 0xE794
2600 op_VPKLS uint32 = 0xE795
2601 op_VPKS uint32 = 0xE797
2602 op_VPERM uint32 = 0xE78C
2603 op_VPDI uint32 = 0xE784
2604 op_VPOPCT uint32 = 0xE750
2605 op_VREP uint32 = 0xE74D
2606 op_VREPI uint32 = 0xE745
2607 op_VSCEF uint32 = 0xE71B
2608 op_VSCEG uint32 = 0xE71A
2609 op_VSEL uint32 = 0xE78D
2610 op_VSL uint32 = 0xE774
2611 op_VSLB uint32 = 0xE775
2612 op_VSLDB uint32 = 0xE777
2613 op_VSRA uint32 = 0xE77E
2614 op_VSRAB uint32 = 0xE77F
2615 op_VSRL uint32 = 0xE77C
2616 op_VSRLB uint32 = 0xE77D
2617 op_VSEG uint32 = 0xE75F
2618 op_VST uint32 = 0xE70E
2619 op_VSTEH uint32 = 0xE709
2620 op_VSTEF uint32 = 0xE70B
2621 op_VSTEG uint32 = 0xE70A
2622 op_VSTEB uint32 = 0xE708
2623 op_VSTM uint32 = 0xE73E
2624 op_VSTL uint32 = 0xE73F
2625 op_VSTRC uint32 = 0xE78A
2626 op_VS uint32 = 0xE7F7
2627 op_VSCBI uint32 = 0xE7F5
2628 op_VSBCBI uint32 = 0xE7BD
2629 op_VSBI uint32 = 0xE7BF
2630 op_VSUMG uint32 = 0xE765
2631 op_VSUMQ uint32 = 0xE767
2632 op_VSUM uint32 = 0xE764
2633 op_VTM uint32 = 0xE7D8
2634 op_VUPH uint32 = 0xE7D7
2635 op_VUPLH uint32 = 0xE7D5
2636 op_VUPLL uint32 = 0xE7D4
2637 op_VUPL uint32 = 0xE7D6
2638 op_VMSL uint32 = 0xE7B8
2639
2640
2641 op_KDSA uint32 = 0xB93A
2642
2643 )
2644
2645 func oclass(a *obj.Addr) int {
2646 return int(a.Class) - 1
2647 }
2648
2649
2650
2651 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) {
2652 if sym == nil {
2653 c.ctxt.Diag("require symbol to apply relocation")
2654 }
2655 offset := int64(2)
2656 c.cursym.AddRel(c.ctxt, obj.Reloc{
2657 Type: objabi.R_PCRELDBL,
2658 Off: int32(c.pc + offset),
2659 Siz: 4,
2660 Sym: sym,
2661 Add: add + offset + 4,
2662 })
2663 }
2664
2665 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) {
2666 if sym == nil {
2667 c.ctxt.Diag("require symbol to apply relocation")
2668 }
2669 offset += int64(2)
2670 c.cursym.AddRel(c.ctxt, obj.Reloc{
2671 Type: objabi.R_PCRELDBL,
2672 Off: int32(c.pc + offset),
2673 Siz: 4,
2674 Sym: sym,
2675 Add: add + offset + 4,
2676 })
2677 }
2678
2679
2680
2681 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) {
2682 if sym == nil {
2683 c.ctxt.Diag("require symbol to apply relocation")
2684 }
2685 offset := int64(2)
2686 c.cursym.AddRel(c.ctxt, obj.Reloc{
2687 Type: objabi.R_CALL,
2688 Off: int32(c.pc + offset),
2689 Siz: 4,
2690 Sym: sym,
2691 Add: add + offset + int64(4),
2692 })
2693 }
2694
2695 func (c *ctxtz) branchMask(p *obj.Prog) CCMask {
2696 switch p.As {
2697 case ABRC, ALOCR, ALOCGR,
2698 ACRJ, ACGRJ, ACIJ, ACGIJ,
2699 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ:
2700 return CCMask(p.From.Offset)
2701 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ:
2702 return Equal
2703 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE:
2704 return GreaterOrEqual
2705 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT:
2706 return Greater
2707 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE:
2708 return LessOrEqual
2709 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT:
2710 return Less
2711 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE:
2712 return NotEqual
2713 case ABLEU:
2714 return NotGreater
2715 case ABLTU:
2716 return LessOrUnordered
2717 case ABVC:
2718 return Never
2719 case ABVS:
2720 return Unordered
2721 }
2722 c.ctxt.Diag("unknown conditional branch %v", p.As)
2723 return Always
2724 }
2725
2726 func regtmp(p *obj.Prog) uint32 {
2727 p.Mark |= USETMP
2728 return REGTMP
2729 }
2730
2731 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
2732 o := c.oplook(p)
2733
2734 if o == nil {
2735 return
2736 }
2737
2738
2739
2740
2741 switch o.i {
2742 default:
2743 c.ctxt.Diag("unknown index %d", o.i)
2744
2745 case 0:
2746 break
2747
2748 case 1:
2749 switch p.As {
2750 default:
2751 c.ctxt.Diag("unhandled operation: %v", p.As)
2752 case AMOVD:
2753 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2754
2755 case AMOVW:
2756 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2757 case AMOVH:
2758 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2759 case AMOVB:
2760 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2761
2762 case AMOVWZ:
2763 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2764 case AMOVHZ:
2765 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2766 case AMOVBZ:
2767 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2768
2769 case AMOVDBR:
2770 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2771 case AMOVWBR:
2772 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2773
2774 case AFMOVD, AFMOVS:
2775 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2776 }
2777
2778 case 2:
2779 r := p.Reg
2780 if r == 0 {
2781 r = p.To.Reg
2782 }
2783
2784 var opcode uint32
2785
2786 switch p.As {
2787 default:
2788 c.ctxt.Diag("invalid opcode")
2789 case AADD:
2790 opcode = op_AGRK
2791 case AADDC:
2792 opcode = op_ALGRK
2793 case AADDE:
2794 opcode = op_ALCGR
2795 case AADDW:
2796 opcode = op_ARK
2797 case AMULLW:
2798 opcode = op_MSGFR
2799 case AMULLD:
2800 opcode = op_MSGR
2801 case ADIVW, AMODW:
2802 opcode = op_DSGFR
2803 case ADIVWU, AMODWU:
2804 opcode = op_DLR
2805 case ADIVD, AMODD:
2806 opcode = op_DSGR
2807 case ADIVDU, AMODDU:
2808 opcode = op_DLGR
2809 }
2810
2811 switch p.As {
2812 default:
2813
2814 case AADD, AADDC, AADDW:
2815 if p.As == AADDW && r == p.To.Reg {
2816 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2817 } else {
2818 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2819 }
2820
2821 case AADDE, AMULLW, AMULLD:
2822 if r == p.To.Reg {
2823 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2824 } else if p.From.Reg == p.To.Reg {
2825 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
2826 } else {
2827 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2828 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2829 }
2830
2831 case ADIVW, ADIVWU, ADIVD, ADIVDU:
2832 if p.As == ADIVWU || p.As == ADIVDU {
2833 zRI(op_LGHI, regtmp(p), 0, asm)
2834 }
2835 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2836 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2837 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm)
2838
2839 case AMODW, AMODWU, AMODD, AMODDU:
2840 if p.As == AMODWU || p.As == AMODDU {
2841 zRI(op_LGHI, regtmp(p), 0, asm)
2842 }
2843 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2844 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2845 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2846
2847 }
2848
2849 case 3:
2850 v := c.vregoff(&p.From)
2851 switch p.As {
2852 case AMOVBZ:
2853 v = int64(uint8(v))
2854 case AMOVHZ:
2855 v = int64(uint16(v))
2856 case AMOVWZ:
2857 v = int64(uint32(v))
2858 case AMOVB:
2859 v = int64(int8(v))
2860 case AMOVH:
2861 v = int64(int16(v))
2862 case AMOVW:
2863 v = int64(int32(v))
2864 }
2865 if int64(int16(v)) == v {
2866 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
2867 } else if v&0xffff0000 == v {
2868 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm)
2869 } else if v&0xffff00000000 == v {
2870 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm)
2871 } else if uint64(v)&0xffff000000000000 == uint64(v) {
2872 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm)
2873 } else if int64(int32(v)) == v {
2874 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm)
2875 } else if int64(uint32(v)) == v {
2876 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2877 } else if uint64(v)&0xffffffff00000000 == uint64(v) {
2878 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2879 } else {
2880 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2881 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2882 }
2883
2884 case 4:
2885 r := p.Reg
2886 if r == 0 {
2887 r = p.To.Reg
2888 }
2889 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2890 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm)
2891 switch p.As {
2892 case AMULHDU:
2893
2894 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2895 case AMULHD:
2896
2897
2898 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm)
2899 zRRE(op_NGR, REGTMP2, uint32(r), asm)
2900 zRRE(op_SGR, regtmp(p), REGTMP2, asm)
2901 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm)
2902 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm)
2903 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm)
2904 }
2905
2906 case 5:
2907 zI(op_SVC, 0, asm)
2908
2909 case 6:
2910 var oprr, oprre, oprrf uint32
2911 switch p.As {
2912 case AAND:
2913 oprre = op_NGR
2914 oprrf = op_NGRK
2915 case AANDW:
2916 oprr = op_NR
2917 oprrf = op_NRK
2918 case AOR:
2919 oprre = op_OGR
2920 oprrf = op_OGRK
2921 case AORW:
2922 oprr = op_OR
2923 oprrf = op_ORK
2924 case AXOR:
2925 oprre = op_XGR
2926 oprrf = op_XGRK
2927 case AXORW:
2928 oprr = op_XR
2929 oprrf = op_XRK
2930 }
2931 if p.Reg == 0 {
2932 if oprr != 0 {
2933 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2934 } else {
2935 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2936 }
2937 } else {
2938 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2939 }
2940
2941 case 7:
2942 d2 := c.vregoff(&p.From)
2943 b2 := p.From.Reg
2944 r3 := p.Reg
2945 if r3 == 0 {
2946 r3 = p.To.Reg
2947 }
2948 r1 := p.To.Reg
2949 var opcode uint32
2950 switch p.As {
2951 default:
2952 case ASLD:
2953 opcode = op_SLLG
2954 case ASRD:
2955 opcode = op_SRLG
2956 case ASLW:
2957 opcode = op_SLLK
2958 case ASRW:
2959 opcode = op_SRLK
2960 case ARLL:
2961 opcode = op_RLL
2962 case ARLLG:
2963 opcode = op_RLLG
2964 case ASRAW:
2965 opcode = op_SRAK
2966 case ASRAD:
2967 opcode = op_SRAG
2968 }
2969 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm)
2970
2971 case 8:
2972 if p.To.Reg&1 != 0 {
2973 c.ctxt.Diag("target must be an even-numbered register")
2974 }
2975
2976 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2977
2978 case 9:
2979 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2980
2981 case 10:
2982 r := int(p.Reg)
2983
2984 switch p.As {
2985 default:
2986 case ASUB:
2987 if r == 0 {
2988 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2989 } else {
2990 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2991 }
2992 case ASUBC:
2993 if r == 0 {
2994 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2995 } else {
2996 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2997 }
2998 case ASUBE:
2999 if r == 0 {
3000 r = int(p.To.Reg)
3001 }
3002 if r == int(p.To.Reg) {
3003 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3004 } else if p.From.Reg == p.To.Reg {
3005 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm)
3006 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3007 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm)
3008 } else {
3009 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3010 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3011 }
3012 case ASUBW:
3013 if r == 0 {
3014 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3015 } else {
3016 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
3017 }
3018 }
3019
3020 case 11:
3021 v := int32(0)
3022
3023 if p.To.Target() != nil {
3024 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3025 }
3026
3027 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v {
3028 zRI(op_BRC, 0xF, uint32(v), asm)
3029 } else {
3030 if p.As == ABL {
3031 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm)
3032 } else {
3033 zRIL(_c, op_BRCL, 0xF, uint32(v), asm)
3034 }
3035 if p.To.Sym != nil {
3036 c.addcallreloc(p.To.Sym, p.To.Offset)
3037 }
3038 }
3039
3040 case 12:
3041 r1 := p.To.Reg
3042 d2 := c.vregoff(&p.From)
3043 b2 := p.From.Reg
3044 if b2 == 0 {
3045 b2 = REGSP
3046 }
3047 x2 := p.From.Index
3048 if -DISP20/2 > d2 || d2 >= DISP20/2 {
3049 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3050 if x2 != 0 {
3051 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3052 }
3053 x2 = int16(regtmp(p))
3054 d2 = 0
3055 }
3056 var opx, opxy uint32
3057 switch p.As {
3058 case AADD:
3059 opxy = op_AG
3060 case AADDC:
3061 opxy = op_ALG
3062 case AADDE:
3063 opxy = op_ALCG
3064 case AADDW:
3065 opx = op_A
3066 opxy = op_AY
3067 case AMULLW:
3068 opx = op_MS
3069 opxy = op_MSY
3070 case AMULLD:
3071 opxy = op_MSG
3072 case ASUB:
3073 opxy = op_SG
3074 case ASUBC:
3075 opxy = op_SLG
3076 case ASUBE:
3077 opxy = op_SLBG
3078 case ASUBW:
3079 opx = op_S
3080 opxy = op_SY
3081 case AAND:
3082 opxy = op_NG
3083 case AANDW:
3084 opx = op_N
3085 opxy = op_NY
3086 case AOR:
3087 opxy = op_OG
3088 case AORW:
3089 opx = op_O
3090 opxy = op_OY
3091 case AXOR:
3092 opxy = op_XG
3093 case AXORW:
3094 opx = op_X
3095 opxy = op_XY
3096 }
3097 if opx != 0 && 0 <= d2 && d2 < DISP12 {
3098 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3099 } else {
3100 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3101 }
3102
3103 case 13:
3104 r1 := p.To.Reg
3105 r2 := p.RestArgs[2].Reg
3106 i3 := uint8(p.From.Offset)
3107 i4 := uint8(p.RestArgs[0].Offset)
3108 i5 := uint8(p.RestArgs[1].Offset)
3109 switch p.As {
3110 case ARNSBGT, ARXSBGT, AROSBGT:
3111 i3 |= 0x80
3112 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ:
3113 i4 |= 0x80
3114 }
3115 var opcode uint32
3116 switch p.As {
3117 case ARNSBG, ARNSBGT:
3118 opcode = op_RNSBG
3119 case ARXSBG, ARXSBGT:
3120 opcode = op_RXSBG
3121 case AROSBG, AROSBGT:
3122 opcode = op_ROSBG
3123 case ARISBG, ARISBGZ:
3124 opcode = op_RISBG
3125 case ARISBGN, ARISBGNZ:
3126 opcode = op_RISBGN
3127 case ARISBHG, ARISBHGZ:
3128 opcode = op_RISBHG
3129 case ARISBLG, ARISBLGZ:
3130 opcode = op_RISBLG
3131 }
3132 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm)
3133
3134 case 15:
3135 r := p.To.Reg
3136 if p.As == ABCL || p.As == ABL {
3137 zRR(op_BASR, uint32(REG_LR), uint32(r), asm)
3138 } else {
3139 zRR(op_BCR, uint32(Always), uint32(r), asm)
3140 }
3141
3142 case 16:
3143 v := int32(0)
3144 if p.To.Target() != nil {
3145 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3146 }
3147 mask := uint32(c.branchMask(p))
3148 if p.To.Sym == nil && int32(int16(v)) == v {
3149 zRI(op_BRC, mask, uint32(v), asm)
3150 } else {
3151 zRIL(_c, op_BRCL, mask, uint32(v), asm)
3152 }
3153 if p.To.Sym != nil {
3154 c.addrilreloc(p.To.Sym, p.To.Offset)
3155 }
3156
3157 case 17:
3158 m3 := uint32(c.branchMask(p))
3159 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3160
3161 case 18:
3162 if p.As == ABL {
3163 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm)
3164 } else {
3165 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm)
3166 }
3167
3168 case 19:
3169 d := c.vregoff(&p.From)
3170 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm)
3171 if d&1 != 0 {
3172 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm)
3173 d -= 1
3174 }
3175 c.addrilreloc(p.From.Sym, d)
3176
3177 case 21:
3178 v := c.vregoff(&p.From)
3179 r := p.Reg
3180 if r == 0 {
3181 r = p.To.Reg
3182 }
3183 switch p.As {
3184 case ASUB:
3185 zRIL(_a, op_LGFI, uint32(regtmp(p)), uint32(v), asm)
3186 zRRF(op_SLGRK, uint32(regtmp(p)), 0, uint32(p.To.Reg), uint32(r), asm)
3187 case ASUBC:
3188 if r != p.To.Reg {
3189 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3190 }
3191 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm)
3192 case ASUBW:
3193 if r != p.To.Reg {
3194 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3195 }
3196 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm)
3197 }
3198
3199 case 22:
3200 v := c.vregoff(&p.From)
3201 r := p.Reg
3202 if r == 0 {
3203 r = p.To.Reg
3204 }
3205 var opri, opril, oprie uint32
3206 switch p.As {
3207 case AADD:
3208 opri = op_AGHI
3209 opril = op_AGFI
3210 oprie = op_AGHIK
3211 case AADDC:
3212 opril = op_ALGFI
3213 oprie = op_ALGHSIK
3214 case AADDW:
3215 opri = op_AHI
3216 opril = op_AFI
3217 oprie = op_AHIK
3218 case AMULLW:
3219 opri = op_MHI
3220 opril = op_MSFI
3221 case AMULLD:
3222 opri = op_MGHI
3223 opril = op_MSGFI
3224 }
3225 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) {
3226 switch p.As {
3227 case AADD, AADDC, AMULLD:
3228 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3229 case AADDW, AMULLW:
3230 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3231 }
3232 r = p.To.Reg
3233 }
3234 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v {
3235 zRI(opri, uint32(p.To.Reg), uint32(v), asm)
3236 } else if oprie != 0 && int64(int16(v)) == v {
3237 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm)
3238 } else {
3239 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm)
3240 }
3241
3242 case 23:
3243
3244 v := c.vregoff(&p.From)
3245 switch p.As {
3246 default:
3247 c.ctxt.Diag("%v is not supported", p)
3248 case AAND:
3249 if v >= 0 {
3250 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3251 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm)
3252 } else if int64(int16(v)) == v {
3253 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3254 } else {
3255 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3256 }
3257 case AOR:
3258 if int64(uint32(v)) != v {
3259 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3260 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm)
3261 } else if int64(uint16(v)) == v {
3262 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3263 } else {
3264 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3265 }
3266 case AXOR:
3267 if int64(uint32(v)) != v {
3268 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3269 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm)
3270 } else {
3271 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3272 }
3273 }
3274
3275 case 24:
3276 v := c.vregoff(&p.From)
3277 switch p.As {
3278 case AANDW:
3279 if uint32(v&0xffff0000) == 0xffff0000 {
3280 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3281 } else if uint32(v&0x0000ffff) == 0x0000ffff {
3282 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3283 } else {
3284 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3285 }
3286 case AORW:
3287 if uint32(v&0xffff0000) == 0 {
3288 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3289 } else if uint32(v&0x0000ffff) == 0 {
3290 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3291 } else {
3292 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3293 }
3294 case AXORW:
3295 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3296 }
3297
3298 case 25:
3299 m3 := uint32(c.branchMask(p))
3300 var opcode uint32
3301 switch p.As {
3302 case ALOCR:
3303 opcode = op_LOCR
3304 case ALOCGR:
3305 opcode = op_LOCGR
3306 }
3307 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3308
3309 case 26:
3310 v := c.regoff(&p.From)
3311 r := p.From.Reg
3312 if r == 0 {
3313 r = REGSP
3314 }
3315 i := p.From.Index
3316 if v >= 0 && v < DISP12 {
3317 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3318 } else if v >= -DISP20/2 && v < DISP20/2 {
3319 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3320 } else {
3321 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3322 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm)
3323 }
3324
3325 case 31:
3326 wd := uint64(c.vregoff(&p.From))
3327 *asm = append(*asm,
3328 uint8(wd>>56),
3329 uint8(wd>>48),
3330 uint8(wd>>40),
3331 uint8(wd>>32),
3332 uint8(wd>>24),
3333 uint8(wd>>16),
3334 uint8(wd>>8),
3335 uint8(wd))
3336
3337 case 32:
3338 var opcode uint32
3339 switch p.As {
3340 default:
3341 c.ctxt.Diag("invalid opcode")
3342 case AFADD:
3343 opcode = op_ADBR
3344 case AFADDS:
3345 opcode = op_AEBR
3346 case AFDIV:
3347 opcode = op_DDBR
3348 case AFDIVS:
3349 opcode = op_DEBR
3350 case AFMUL:
3351 opcode = op_MDBR
3352 case AFMULS:
3353 opcode = op_MEEBR
3354 case AFSUB:
3355 opcode = op_SDBR
3356 case AFSUBS:
3357 opcode = op_SEBR
3358 }
3359 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3360
3361 case 33:
3362 r := p.From.Reg
3363 if oclass(&p.From) == C_NONE {
3364 r = p.To.Reg
3365 }
3366 var opcode uint32
3367 switch p.As {
3368 default:
3369 case AFABS:
3370 opcode = op_LPDBR
3371 case AFNABS:
3372 opcode = op_LNDBR
3373 case ALPDFR:
3374 opcode = op_LPDFR
3375 case ALNDFR:
3376 opcode = op_LNDFR
3377 case AFNEG:
3378 opcode = op_LCDFR
3379 case AFNEGS:
3380 opcode = op_LCEBR
3381 case ALCDBR:
3382 opcode = op_LCDBR
3383 case ALEDBR:
3384 opcode = op_LEDBR
3385 case ALDEBR:
3386 opcode = op_LDEBR
3387 case AFSQRT:
3388 opcode = op_SQDBR
3389 case AFSQRTS:
3390 opcode = op_SQEBR
3391 }
3392 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
3393
3394 case 34:
3395 var opcode uint32
3396 switch p.As {
3397 default:
3398 c.ctxt.Diag("invalid opcode")
3399 case AFMADD:
3400 opcode = op_MADBR
3401 case AFMADDS:
3402 opcode = op_MAEBR
3403 case AFMSUB:
3404 opcode = op_MSDBR
3405 case AFMSUBS:
3406 opcode = op_MSEBR
3407 }
3408 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
3409
3410 case 35:
3411 d2 := c.regoff(&p.To)
3412 b2 := p.To.Reg
3413 if b2 == 0 {
3414 b2 = REGSP
3415 }
3416 x2 := p.To.Index
3417 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3418 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3419 if x2 != 0 {
3420 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3421 }
3422 x2 = int16(regtmp(p))
3423 d2 = 0
3424 }
3425
3426 if op, ok := c.zopstore12(p.As); ok && isU12(d2) {
3427 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3428 } else {
3429 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3430 }
3431
3432 case 36:
3433 d2 := c.regoff(&p.From)
3434 b2 := p.From.Reg
3435 if b2 == 0 {
3436 b2 = REGSP
3437 }
3438 x2 := p.From.Index
3439 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3440 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3441 if x2 != 0 {
3442 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3443 }
3444 x2 = int16(regtmp(p))
3445 d2 = 0
3446 }
3447
3448 if op, ok := c.zopload12(p.As); ok && isU12(d2) {
3449 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3450 } else {
3451 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3452 }
3453
3454 case 40:
3455 wd := uint32(c.regoff(&p.From))
3456 if p.As == AWORD {
3457 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd))
3458 } else {
3459 *asm = append(*asm, uint8(wd))
3460 }
3461
3462 case 41:
3463 r1 := p.From.Reg
3464 ri2 := (p.To.Target().Pc - p.Pc) >> 1
3465 if int64(int16(ri2)) != ri2 {
3466 c.ctxt.Diag("branch target too far away")
3467 }
3468 var opcode uint32
3469 switch p.As {
3470 case ABRCT:
3471 opcode = op_BRCT
3472 case ABRCTG:
3473 opcode = op_BRCTG
3474 }
3475 zRI(opcode, uint32(r1), uint32(ri2), asm)
3476
3477 case 47:
3478 r := p.From.Reg
3479 if r == 0 {
3480 r = p.To.Reg
3481 }
3482 switch p.As {
3483 case ANEG:
3484 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
3485 case ANEGW:
3486 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm)
3487 }
3488
3489 case 48:
3490 m3 := c.vregoff(&p.From)
3491 if 0 > m3 || m3 > 7 {
3492 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3)
3493 }
3494 var opcode uint32
3495 switch p.As {
3496 case AFIEBR:
3497 opcode = op_FIEBR
3498 case AFIDBR:
3499 opcode = op_FIDBR
3500 }
3501 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3502
3503 case 49:
3504 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3505
3506 case 50:
3507 var opcode uint32
3508 switch p.As {
3509 case ALTEBR:
3510 opcode = op_LTEBR
3511 case ALTDBR:
3512 opcode = op_LTDBR
3513 }
3514 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3515
3516 case 51:
3517 var opcode uint32
3518 switch p.As {
3519 case ATCEB:
3520 opcode = op_TCEB
3521 case ATCDB:
3522 opcode = op_TCDB
3523 }
3524 d2 := c.regoff(&p.To)
3525 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm)
3526
3527 case 62:
3528 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3529
3530 case 66:
3531 zRR(op_BCR, uint32(Never), 0, asm)
3532
3533 case 67:
3534 var opcode uint32
3535 switch p.As {
3536 case AFMOVS:
3537 opcode = op_LZER
3538 case AFMOVD:
3539 opcode = op_LZDR
3540 }
3541 zRRE(opcode, uint32(p.To.Reg), 0, asm)
3542
3543 case 68:
3544 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm)
3545
3546 case 69:
3547 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm)
3548
3549 case 70:
3550 if p.As == ACMPW || p.As == ACMPWU {
3551 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3552 } else {
3553 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3554 }
3555
3556 case 71:
3557 v := c.vregoff(&p.To)
3558 switch p.As {
3559 case ACMP, ACMPW:
3560 if int64(int32(v)) != v {
3561 c.ctxt.Diag("%v overflows an int32", v)
3562 }
3563 case ACMPU, ACMPWU:
3564 if int64(uint32(v)) != v {
3565 c.ctxt.Diag("%v overflows a uint32", v)
3566 }
3567 }
3568 if p.As == ACMP && int64(int16(v)) == v {
3569 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm)
3570 } else if p.As == ACMPW && int64(int16(v)) == v {
3571 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm)
3572 } else {
3573 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm)
3574 }
3575
3576 case 72:
3577 v := c.regoff(&p.From)
3578 d := c.regoff(&p.To)
3579 r := p.To.Reg
3580 if p.To.Index != 0 {
3581 c.ctxt.Diag("cannot use index register")
3582 }
3583 if r == 0 {
3584 r = REGSP
3585 }
3586 var opcode uint32
3587 switch p.As {
3588 case AMOVD:
3589 opcode = op_MVGHI
3590 case AMOVW, AMOVWZ:
3591 opcode = op_MVHI
3592 case AMOVH, AMOVHZ:
3593 opcode = op_MVHHI
3594 case AMOVB, AMOVBZ:
3595 opcode = op_MVI
3596 }
3597 if d < 0 || d >= DISP12 {
3598 if r == int16(regtmp(p)) {
3599 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r)
3600 }
3601 if d >= -DISP20/2 && d < DISP20/2 {
3602 if opcode == op_MVI {
3603 opcode = op_MVIY
3604 } else {
3605 zRXY(op_LAY, uint32(regtmp(p)), 0, uint32(r), uint32(d), asm)
3606 r = int16(regtmp(p))
3607 d = 0
3608 }
3609 } else {
3610 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm)
3611 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm)
3612 r = int16(regtmp(p))
3613 d = 0
3614 }
3615 }
3616 switch opcode {
3617 case op_MVI:
3618 zSI(opcode, uint32(v), uint32(r), uint32(d), asm)
3619 case op_MVIY:
3620 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm)
3621 default:
3622 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm)
3623 }
3624
3625 case 73:
3626 zE(op_BRRK, asm)
3627
3628 case 74:
3629 i2 := c.regoff(&p.To)
3630 switch p.As {
3631 case AMOVD:
3632 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm)
3633 case AMOVW, AMOVWZ:
3634 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm)
3635 case AMOVH, AMOVHZ:
3636 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm)
3637 case AMOVB, AMOVBZ:
3638 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3639 adj := uint32(0)
3640 if i2&1 != 0 {
3641 i2 -= 1
3642 adj = 1
3643 }
3644 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm)
3645 case AFMOVD:
3646 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3647 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3648 case AFMOVS:
3649 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3650 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3651 }
3652 c.addrilreloc(p.To.Sym, int64(i2))
3653
3654 case 75:
3655 i2 := c.regoff(&p.From)
3656 switch p.As {
3657 case AMOVD:
3658 if i2&1 != 0 {
3659 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3660 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm)
3661 i2 -= 1
3662 } else {
3663 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3664 }
3665 case AMOVW:
3666 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm)
3667 case AMOVWZ:
3668 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm)
3669 case AMOVH:
3670 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm)
3671 case AMOVHZ:
3672 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm)
3673 case AMOVB, AMOVBZ:
3674 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3675 adj := uint32(0)
3676 if i2&1 != 0 {
3677 i2 -= 1
3678 adj = 1
3679 }
3680 switch p.As {
3681 case AMOVB:
3682 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3683 case AMOVBZ:
3684 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3685 }
3686 case AFMOVD:
3687 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3688 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3689 case AFMOVS:
3690 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3691 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3692 }
3693 c.addrilreloc(p.From.Sym, int64(i2))
3694
3695 case 76:
3696 zRR(op_SPM, uint32(p.From.Reg), 0, asm)
3697
3698 case 77:
3699 if p.From.Offset > 255 || p.From.Offset < 1 {
3700 c.ctxt.Diag("illegal system call; system call number out of range: %v", p)
3701 zE(op_TRAP2, asm)
3702 } else {
3703 zI(op_SVC, uint32(p.From.Offset), asm)
3704 }
3705
3706 case 78:
3707
3708
3709 *asm = append(*asm, 0, 0, 0, 0)
3710
3711 case 79:
3712 v := c.regoff(&p.To)
3713 if v < 0 {
3714 v = 0
3715 }
3716 if p.As == ACS {
3717 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3718 } else if p.As == ACSG {
3719 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3720 }
3721
3722 case 80:
3723 zRR(op_BCR, 14, 0, asm)
3724
3725 case 81:
3726 switch p.As {
3727 case ALDGR:
3728 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3729 case ALGDR:
3730 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3731 }
3732
3733 case 82:
3734 var opcode uint32
3735 switch p.As {
3736 default:
3737 log.Fatalf("unexpected opcode %v", p.As)
3738 case ACEFBRA:
3739 opcode = op_CEFBRA
3740 case ACDFBRA:
3741 opcode = op_CDFBRA
3742 case ACEGBRA:
3743 opcode = op_CEGBRA
3744 case ACDGBRA:
3745 opcode = op_CDGBRA
3746 case ACELFBR:
3747 opcode = op_CELFBR
3748 case ACDLFBR:
3749 opcode = op_CDLFBR
3750 case ACELGBR:
3751 opcode = op_CELGBR
3752 case ACDLGBR:
3753 opcode = op_CDLGBR
3754 }
3755
3756
3757
3758
3759 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3760
3761 case 83:
3762 var opcode uint32
3763 switch p.As {
3764 default:
3765 log.Fatalf("unexpected opcode %v", p.As)
3766 case ACFEBRA:
3767 opcode = op_CFEBRA
3768 case ACFDBRA:
3769 opcode = op_CFDBRA
3770 case ACGEBRA:
3771 opcode = op_CGEBRA
3772 case ACGDBRA:
3773 opcode = op_CGDBRA
3774 case ACLFEBR:
3775 opcode = op_CLFEBR
3776 case ACLFDBR:
3777 opcode = op_CLFDBR
3778 case ACLGEBR:
3779 opcode = op_CLGEBR
3780 case ACLGDBR:
3781 opcode = op_CLGDBR
3782 }
3783
3784
3785 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3786
3787 case 84:
3788 l := c.regoff(&p.From)
3789 if l < 1 || l > 256 {
3790 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l)
3791 }
3792 if p.GetFrom3().Index != 0 || p.To.Index != 0 {
3793 c.ctxt.Diag("cannot use index reg")
3794 }
3795 b1 := p.To.Reg
3796 b2 := p.GetFrom3().Reg
3797 if b1 == 0 {
3798 b1 = REGSP
3799 }
3800 if b2 == 0 {
3801 b2 = REGSP
3802 }
3803 d1 := c.regoff(&p.To)
3804 d2 := c.regoff(p.GetFrom3())
3805 if d1 < 0 || d1 >= DISP12 {
3806 if b2 == int16(regtmp(p)) {
3807 c.ctxt.Diag("regtmp(p) conflict")
3808 }
3809 if b1 != int16(regtmp(p)) {
3810 zRRE(op_LGR, regtmp(p), uint32(b1), asm)
3811 }
3812 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm)
3813 if d1 == d2 && b1 == b2 {
3814 d2 = 0
3815 b2 = int16(regtmp(p))
3816 }
3817 d1 = 0
3818 b1 = int16(regtmp(p))
3819 }
3820 if d2 < 0 || d2 >= DISP12 {
3821 if b1 == REGTMP2 {
3822 c.ctxt.Diag("REGTMP2 conflict")
3823 }
3824 if b2 != REGTMP2 {
3825 zRRE(op_LGR, REGTMP2, uint32(b2), asm)
3826 }
3827 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm)
3828 d2 = 0
3829 b2 = REGTMP2
3830 }
3831 var opcode uint32
3832 switch p.As {
3833 default:
3834 c.ctxt.Diag("unexpected opcode %v", p.As)
3835 case AMVC:
3836 opcode = op_MVC
3837 case AMVCIN:
3838 opcode = op_MVCIN
3839 case ACLC:
3840 opcode = op_CLC
3841
3842 b1, b2 = b2, b1
3843 d1, d2 = d2, d1
3844 case AXC:
3845 opcode = op_XC
3846 case AOC:
3847 opcode = op_OC
3848 case ANC:
3849 opcode = op_NC
3850 }
3851 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm)
3852
3853 case 85:
3854 v := c.regoff(&p.From)
3855 if p.From.Sym == nil {
3856 if (v & 1) != 0 {
3857 c.ctxt.Diag("cannot use LARL with odd offset: %v", v)
3858 }
3859 } else {
3860 c.addrilreloc(p.From.Sym, int64(v))
3861 v = 0
3862 }
3863 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm)
3864
3865 case 86:
3866 d := c.vregoff(&p.From)
3867 x := p.From.Index
3868 b := p.From.Reg
3869 if b == 0 {
3870 b = REGSP
3871 }
3872 switch p.As {
3873 case ALA:
3874 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3875 case ALAY:
3876 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3877 }
3878
3879 case 87:
3880 v := c.vregoff(&p.From)
3881 if p.From.Sym == nil {
3882 if v&1 != 0 {
3883 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v)
3884 }
3885 } else {
3886 c.addrilreloc(p.From.Sym, v)
3887 v = 0
3888 }
3889 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm)
3890
3891 case 88:
3892 var opcode uint32
3893 switch p.As {
3894 case ASTCK:
3895 opcode = op_STCK
3896 case ASTCKC:
3897 opcode = op_STCKC
3898 case ASTCKE:
3899 opcode = op_STCKE
3900 case ASTCKF:
3901 opcode = op_STCKF
3902 }
3903 v := c.vregoff(&p.To)
3904 r := p.To.Reg
3905 if r == 0 {
3906 r = REGSP
3907 }
3908 zS(opcode, uint32(r), uint32(v), asm)
3909
3910 case 89:
3911 var v int32
3912 if p.To.Target() != nil {
3913 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3914 }
3915
3916
3917 r1, r2 := p.From.Reg, p.Reg
3918 if p.From.Type == obj.TYPE_CONST {
3919 r1, r2 = p.Reg, p.RestArgs[0].Reg
3920 }
3921 m3 := uint32(c.branchMask(p))
3922
3923 var opcode uint32
3924 switch p.As {
3925 case ACRJ:
3926
3927 opcode = op_CRJ
3928 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3929
3930 opcode = op_CGRJ
3931 case ACLRJ:
3932
3933 opcode = op_CLRJ
3934 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3935
3936 opcode = op_CLGRJ
3937 }
3938
3939 if int32(int16(v)) != v {
3940
3941
3942
3943
3944
3945
3946
3947
3948 m3 ^= 0xe
3949 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm)
3950 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3951 } else {
3952 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm)
3953 }
3954
3955 case 90:
3956 var v int32
3957 if p.To.Target() != nil {
3958 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3959 }
3960
3961
3962 r1, i2 := p.From.Reg, p.RestArgs[0].Offset
3963 if p.From.Type == obj.TYPE_CONST {
3964 r1 = p.Reg
3965 }
3966 m3 := uint32(c.branchMask(p))
3967
3968 var opcode uint32
3969 switch p.As {
3970 case ACIJ:
3971 opcode = op_CIJ
3972 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3973 opcode = op_CGIJ
3974 case ACLIJ:
3975 opcode = op_CLIJ
3976 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3977 opcode = op_CLGIJ
3978 }
3979 if int32(int16(v)) != v {
3980
3981
3982
3983
3984
3985
3986
3987
3988 m3 ^= 0xe
3989 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm)
3990 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3991 } else {
3992 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm)
3993 }
3994
3995 case 91:
3996 var opcode uint32
3997 switch p.As {
3998 case ATMHH:
3999 opcode = op_TMHH
4000 case ATMHL:
4001 opcode = op_TMHL
4002 case ATMLH:
4003 opcode = op_TMLH
4004 case ATMLL:
4005 opcode = op_TMLL
4006 }
4007 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm)
4008
4009 case 92:
4010 zRRE(op_IPM, uint32(p.From.Reg), 0, asm)
4011
4012 case 93:
4013 v := c.vregoff(&p.To)
4014 if v != 0 {
4015 c.ctxt.Diag("invalid offset against GOT slot %v", p)
4016 }
4017 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
4018 c.cursym.AddRel(c.ctxt, obj.Reloc{
4019 Type: objabi.R_GOTPCREL,
4020 Off: int32(c.pc + 2),
4021 Siz: 4,
4022 Sym: p.From.Sym,
4023 Add: 2 + 4,
4024 })
4025
4026 case 94:
4027 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm)
4028 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4029 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm)
4030 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0)
4031 c.cursym.AddRel(c.ctxt, obj.Reloc{
4032 Type: objabi.R_TLS_LE,
4033 Off: int32(c.pc + sizeRIL + sizeRXY + sizeRI),
4034 Siz: 8,
4035 Sym: p.From.Sym,
4036 })
4037
4038 case 95:
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050 zRIL(_b, op_LARL, regtmp(p), 0, asm)
4051 c.cursym.AddRel(c.ctxt, obj.Reloc{
4052 Type: objabi.R_TLS_IE,
4053 Off: int32(c.pc + 2),
4054 Siz: 4,
4055 Sym: p.From.Sym,
4056 Add: 2 + 4,
4057 })
4058
4059
4060 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4061
4062
4063
4064 case 96:
4065 length := c.vregoff(&p.From)
4066 offset := c.vregoff(&p.To)
4067 reg := p.To.Reg
4068 if reg == 0 {
4069 reg = REGSP
4070 }
4071 if length <= 0 {
4072 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length)
4073 }
4074 for length > 0 {
4075 if offset < 0 || offset >= DISP12 {
4076 if offset >= -DISP20/2 && offset < DISP20/2 {
4077 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm)
4078 } else {
4079 if reg != int16(regtmp(p)) {
4080 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4081 }
4082 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4083 }
4084 reg = int16(regtmp(p))
4085 offset = 0
4086 }
4087 size := length
4088 if size > 256 {
4089 size = 256
4090 }
4091
4092 switch size {
4093 case 1:
4094 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm)
4095 case 2:
4096 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm)
4097 case 4:
4098 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm)
4099 case 8:
4100 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm)
4101 default:
4102 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm)
4103 }
4104
4105 length -= size
4106 offset += size
4107 }
4108
4109 case 97:
4110 rstart := p.From.Reg
4111 rend := p.Reg
4112 offset := c.regoff(&p.To)
4113 reg := p.To.Reg
4114 if reg == 0 {
4115 reg = REGSP
4116 }
4117 if offset < -DISP20/2 || offset >= DISP20/2 {
4118 if reg != int16(regtmp(p)) {
4119 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4120 }
4121 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4122 reg = int16(regtmp(p))
4123 offset = 0
4124 }
4125 switch p.As {
4126 case ASTMY:
4127 if offset >= 0 && offset < DISP12 {
4128 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4129 } else {
4130 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4131 }
4132 case ASTMG:
4133 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4134 }
4135
4136 case 98:
4137 rstart := p.Reg
4138 rend := p.To.Reg
4139 offset := c.regoff(&p.From)
4140 reg := p.From.Reg
4141 if reg == 0 {
4142 reg = REGSP
4143 }
4144 if offset < -DISP20/2 || offset >= DISP20/2 {
4145 if reg != int16(regtmp(p)) {
4146 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4147 }
4148 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4149 reg = int16(regtmp(p))
4150 offset = 0
4151 }
4152 switch p.As {
4153 case ALMY:
4154 if offset >= 0 && offset < DISP12 {
4155 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4156 } else {
4157 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4158 }
4159 case ALMG:
4160 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4161 }
4162
4163 case 99:
4164 if p.To.Index != 0 {
4165 c.ctxt.Diag("cannot use indexed address")
4166 }
4167 offset := c.regoff(&p.To)
4168 if offset < -DISP20/2 || offset >= DISP20/2 {
4169 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset)
4170 }
4171 var opcode uint32
4172 switch p.As {
4173 case ALAA:
4174 opcode = op_LAA
4175 case ALAAG:
4176 opcode = op_LAAG
4177 case ALAAL:
4178 opcode = op_LAAL
4179 case ALAALG:
4180 opcode = op_LAALG
4181 case ALAN:
4182 opcode = op_LAN
4183 case ALANG:
4184 opcode = op_LANG
4185 case ALAX:
4186 opcode = op_LAX
4187 case ALAXG:
4188 opcode = op_LAXG
4189 case ALAO:
4190 opcode = op_LAO
4191 case ALAOG:
4192 opcode = op_LAOG
4193 }
4194 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm)
4195
4196 case 100:
4197 op, m3, _ := vop(p.As)
4198 v1 := p.From.Reg
4199 if p.Reg != 0 {
4200 m3 = uint32(c.vregoff(&p.From))
4201 v1 = p.Reg
4202 }
4203 b2 := p.To.Reg
4204 if b2 == 0 {
4205 b2 = REGSP
4206 }
4207 d2 := uint32(c.vregoff(&p.To))
4208 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4209
4210 case 101:
4211 op, m3, _ := vop(p.As)
4212 src := &p.From
4213 if p.GetFrom3() != nil {
4214 m3 = uint32(c.vregoff(&p.From))
4215 src = p.GetFrom3()
4216 }
4217 b2 := src.Reg
4218 if b2 == 0 {
4219 b2 = REGSP
4220 }
4221 d2 := uint32(c.vregoff(src))
4222 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm)
4223
4224 case 102:
4225 op, _, _ := vop(p.As)
4226 m3 := uint32(c.vregoff(&p.From))
4227 b2 := p.To.Reg
4228 if b2 == 0 {
4229 b2 = REGSP
4230 }
4231 d2 := uint32(c.vregoff(&p.To))
4232 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4233
4234 case 103:
4235 op, _, _ := vop(p.As)
4236 m3 := uint32(c.vregoff(&p.From))
4237 b2 := p.GetFrom3().Reg
4238 if b2 == 0 {
4239 b2 = REGSP
4240 }
4241 d2 := uint32(c.vregoff(p.GetFrom3()))
4242 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm)
4243
4244 case 104:
4245 op, m4, _ := vop(p.As)
4246 fr := p.Reg
4247 if fr == 0 {
4248 fr = p.To.Reg
4249 }
4250 bits := uint32(c.vregoff(&p.From))
4251 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm)
4252
4253 case 105:
4254 op, _, _ := vop(p.As)
4255 offset := uint32(c.vregoff(&p.To))
4256 reg := p.To.Reg
4257 if reg == 0 {
4258 reg = REGSP
4259 }
4260 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm)
4261
4262 case 106:
4263 op, _, _ := vop(p.As)
4264 offset := uint32(c.vregoff(&p.From))
4265 reg := p.From.Reg
4266 if reg == 0 {
4267 reg = REGSP
4268 }
4269 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm)
4270
4271 case 107:
4272 op, _, _ := vop(p.As)
4273 offset := uint32(c.vregoff(&p.To))
4274 reg := p.To.Reg
4275 if reg == 0 {
4276 reg = REGSP
4277 }
4278 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4279
4280 case 108:
4281 op, _, _ := vop(p.As)
4282 offset := uint32(c.vregoff(p.GetFrom3()))
4283 reg := p.GetFrom3().Reg
4284 if reg == 0 {
4285 reg = REGSP
4286 }
4287 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4288
4289 case 109:
4290 op, m3, _ := vop(p.As)
4291 i2 := uint32(c.vregoff(&p.From))
4292 if p.GetFrom3() != nil {
4293 m3 = uint32(c.vregoff(&p.From))
4294 i2 = uint32(c.vregoff(p.GetFrom3()))
4295 }
4296 switch p.As {
4297 case AVZERO:
4298 i2 = 0
4299 case AVONE:
4300 i2 = 0xffff
4301 }
4302 zVRIa(op, uint32(p.To.Reg), i2, m3, asm)
4303
4304 case 110:
4305 op, m4, _ := vop(p.As)
4306 i2 := uint32(c.vregoff(&p.From))
4307 i3 := uint32(c.vregoff(p.GetFrom3()))
4308 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm)
4309
4310 case 111:
4311 op, m4, _ := vop(p.As)
4312 i2 := uint32(c.vregoff(&p.From))
4313 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm)
4314
4315 case 112:
4316 op, m5, _ := vop(p.As)
4317 i4 := uint32(c.vregoff(&p.From))
4318 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm)
4319
4320 case 113:
4321 op, m4, _ := vop(p.As)
4322 m5 := singleElementMask(p.As)
4323 i3 := uint32(c.vregoff(&p.From))
4324 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm)
4325
4326 case 114:
4327 op, m3, m5 := vop(p.As)
4328 m4 := singleElementMask(p.As)
4329 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm)
4330
4331 case 115:
4332 op, m3, m5 := vop(p.As)
4333 m4 := singleElementMask(p.As)
4334 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm)
4335
4336 case 117:
4337 op, m4, m5 := vop(p.As)
4338 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm)
4339
4340 case 118:
4341 op, m4, m6 := vop(p.As)
4342 m5 := singleElementMask(p.As)
4343 v3 := p.Reg
4344 if v3 == 0 {
4345 v3 = p.To.Reg
4346 }
4347 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm)
4348
4349 case 119:
4350 op, m4, m6 := vop(p.As)
4351 m5 := singleElementMask(p.As)
4352 v2 := p.Reg
4353 if v2 == 0 {
4354 v2 = p.To.Reg
4355 }
4356 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm)
4357
4358 case 120:
4359 op, m6, m5 := vop(p.As)
4360 v1 := uint32(p.To.Reg)
4361 v2 := uint32(p.From.Reg)
4362 v3 := uint32(p.Reg)
4363 v4 := uint32(p.GetFrom3().Reg)
4364 zVRRd(op, v1, v2, v3, m6, m5, v4, asm)
4365
4366 case 121:
4367 op, m6, _ := vop(p.As)
4368 m5 := singleElementMask(p.As)
4369 v1 := uint32(p.To.Reg)
4370 v2 := uint32(p.From.Reg)
4371 v3 := uint32(p.Reg)
4372 v4 := uint32(p.GetFrom3().Reg)
4373 zVRRe(op, v1, v2, v3, m6, m5, v4, asm)
4374
4375 case 122:
4376 op, _, _ := vop(p.As)
4377 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
4378
4379 case 123:
4380 op, _, _ := vop(p.As)
4381 m4 := c.regoff(&p.From)
4382 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm)
4383
4384 case 124:
4385 var opcode uint32
4386 switch p.As {
4387 default:
4388 c.ctxt.Diag("unexpected opcode %v", p.As)
4389 case AKM, AKMC, AKLMD:
4390 if p.From.Reg == REG_R0 {
4391 c.ctxt.Diag("input must not be R0 in %v", p)
4392 }
4393 if p.From.Reg&1 != 0 {
4394 c.ctxt.Diag("input must be even register in %v", p)
4395 }
4396 if p.To.Reg == REG_R0 {
4397 c.ctxt.Diag("second argument must not be R0 in %v", p)
4398 }
4399 if p.To.Reg&1 != 0 {
4400 c.ctxt.Diag("second argument must be even register in %v", p)
4401 }
4402 if p.As == AKM {
4403 opcode = op_KM
4404 } else if p.As == AKMC {
4405 opcode = op_KMC
4406 } else {
4407 opcode = op_KLMD
4408 }
4409 case AKIMD:
4410 if p.To.Reg == REG_R0 {
4411 c.ctxt.Diag("second argument must not be R0 in %v", p)
4412 }
4413 if p.To.Reg&1 != 0 {
4414 c.ctxt.Diag("second argument must be even register in %v", p)
4415 }
4416 opcode = op_KIMD
4417 }
4418 zRRE(opcode, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4419
4420 case 125:
4421 if p.To.Reg == REG_R0 {
4422 c.ctxt.Diag("second argument must not be R0 in %v", p)
4423 }
4424 if p.To.Reg&1 != 0 {
4425 c.ctxt.Diag("second argument must be an even register in %v", p)
4426 }
4427 zRRE(op_KDSA, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4428
4429 case 126:
4430 var opcode uint32
4431 switch p.As {
4432 default:
4433 c.ctxt.Diag("unexpected opcode %v", p.As)
4434 case AKMA, AKMCTR:
4435 if p.From.Reg == REG_R0 {
4436 c.ctxt.Diag("input argument must not be R0 in %v", p)
4437 }
4438 if p.From.Reg&1 != 0 {
4439 c.ctxt.Diag("input argument must be even register in %v", p)
4440 }
4441 if p.To.Reg == REG_R0 {
4442 c.ctxt.Diag("output argument must not be R0 in %v", p)
4443 }
4444 if p.To.Reg&1 != 0 {
4445 c.ctxt.Diag("output argument must be an even register in %v", p)
4446 }
4447 if p.Reg == REG_R0 {
4448 c.ctxt.Diag("third argument must not be R0 in %v", p)
4449 }
4450 if p.Reg&1 != 0 {
4451 c.ctxt.Diag("third argument must be even register in %v", p)
4452 }
4453 if p.As == AKMA {
4454 opcode = op_KMA
4455 } else if p.As == AKMCTR {
4456 opcode = op_KMCTR
4457 }
4458 }
4459 zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4460
4461 case 127:
4462
4463
4464
4465
4466
4467 d2 := c.regoff(&p.From)
4468 if p.To.Reg&1 != 0 {
4469 c.ctxt.Diag("output argument must be even register in %v", p)
4470 }
4471 if p.Reg&1 != 0 {
4472 c.ctxt.Diag("input argument must be an even register in %v", p)
4473 }
4474 if (p.From.Reg == p.To.Reg) || (p.From.Reg == p.Reg) {
4475 c.ctxt.Diag("padding byte register cannot be same as input or output register %v", p)
4476 }
4477 zRS(op_MVCLE, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), uint32(d2), asm)
4478 }
4479 }
4480
4481 func (c *ctxtz) vregoff(a *obj.Addr) int64 {
4482 c.instoffset = 0
4483 if a != nil {
4484 c.aclass(a)
4485 }
4486 return c.instoffset
4487 }
4488
4489 func (c *ctxtz) regoff(a *obj.Addr) int32 {
4490 return int32(c.vregoff(a))
4491 }
4492
4493
4494 func isU12(displacement int32) bool {
4495 return displacement >= 0 && displacement < DISP12
4496 }
4497
4498
4499 func (c *ctxtz) zopload12(a obj.As) (uint32, bool) {
4500 switch a {
4501 case AFMOVD:
4502 return op_LD, true
4503 case AFMOVS:
4504 return op_LE, true
4505 }
4506 return 0, false
4507 }
4508
4509
4510 func (c *ctxtz) zopload(a obj.As) uint32 {
4511 switch a {
4512
4513 case AMOVD:
4514 return op_LG
4515 case AMOVW:
4516 return op_LGF
4517 case AMOVWZ:
4518 return op_LLGF
4519 case AMOVH:
4520 return op_LGH
4521 case AMOVHZ:
4522 return op_LLGH
4523 case AMOVB:
4524 return op_LGB
4525 case AMOVBZ:
4526 return op_LLGC
4527
4528
4529 case AFMOVD:
4530 return op_LDY
4531 case AFMOVS:
4532 return op_LEY
4533
4534
4535 case AMOVDBR:
4536 return op_LRVG
4537 case AMOVWBR:
4538 return op_LRV
4539 case AMOVHBR:
4540 return op_LRVH
4541 }
4542
4543 c.ctxt.Diag("unknown store opcode %v", a)
4544 return 0
4545 }
4546
4547
4548 func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) {
4549 switch a {
4550 case AFMOVD:
4551 return op_STD, true
4552 case AFMOVS:
4553 return op_STE, true
4554 case AMOVW, AMOVWZ:
4555 return op_ST, true
4556 case AMOVH, AMOVHZ:
4557 return op_STH, true
4558 case AMOVB, AMOVBZ:
4559 return op_STC, true
4560 }
4561 return 0, false
4562 }
4563
4564
4565 func (c *ctxtz) zopstore(a obj.As) uint32 {
4566 switch a {
4567
4568 case AMOVD:
4569 return op_STG
4570 case AMOVW, AMOVWZ:
4571 return op_STY
4572 case AMOVH, AMOVHZ:
4573 return op_STHY
4574 case AMOVB, AMOVBZ:
4575 return op_STCY
4576
4577
4578 case AFMOVD:
4579 return op_STDY
4580 case AFMOVS:
4581 return op_STEY
4582
4583
4584 case AMOVDBR:
4585 return op_STRVG
4586 case AMOVWBR:
4587 return op_STRV
4588 case AMOVHBR:
4589 return op_STRVH
4590 }
4591
4592 c.ctxt.Diag("unknown store opcode %v", a)
4593 return 0
4594 }
4595
4596
4597 func (c *ctxtz) zoprre(a obj.As) uint32 {
4598 switch a {
4599 case ACMP:
4600 return op_CGR
4601 case ACMPU:
4602 return op_CLGR
4603 case AFCMPO:
4604 return op_KDBR
4605 case AFCMPU:
4606 return op_CDBR
4607 case ACEBR:
4608 return op_CEBR
4609 }
4610 c.ctxt.Diag("unknown rre opcode %v", a)
4611 return 0
4612 }
4613
4614
4615 func (c *ctxtz) zoprr(a obj.As) uint32 {
4616 switch a {
4617 case ACMPW:
4618 return op_CR
4619 case ACMPWU:
4620 return op_CLR
4621 }
4622 c.ctxt.Diag("unknown rr opcode %v", a)
4623 return 0
4624 }
4625
4626
4627 func (c *ctxtz) zopril(a obj.As) uint32 {
4628 switch a {
4629 case ACMP:
4630 return op_CGFI
4631 case ACMPU:
4632 return op_CLGFI
4633 case ACMPW:
4634 return op_CFI
4635 case ACMPWU:
4636 return op_CLFI
4637 }
4638 c.ctxt.Diag("unknown ril opcode %v", a)
4639 return 0
4640 }
4641
4642
4643 const (
4644 sizeE = 2
4645 sizeI = 2
4646 sizeIE = 4
4647 sizeMII = 6
4648 sizeRI = 4
4649 sizeRI1 = 4
4650 sizeRI2 = 4
4651 sizeRI3 = 4
4652 sizeRIE = 6
4653 sizeRIE1 = 6
4654 sizeRIE2 = 6
4655 sizeRIE3 = 6
4656 sizeRIE4 = 6
4657 sizeRIE5 = 6
4658 sizeRIE6 = 6
4659 sizeRIL = 6
4660 sizeRIL1 = 6
4661 sizeRIL2 = 6
4662 sizeRIL3 = 6
4663 sizeRIS = 6
4664 sizeRR = 2
4665 sizeRRD = 4
4666 sizeRRE = 4
4667 sizeRRF = 4
4668 sizeRRF1 = 4
4669 sizeRRF2 = 4
4670 sizeRRF3 = 4
4671 sizeRRF4 = 4
4672 sizeRRF5 = 4
4673 sizeRRR = 2
4674 sizeRRS = 6
4675 sizeRS = 4
4676 sizeRS1 = 4
4677 sizeRS2 = 4
4678 sizeRSI = 4
4679 sizeRSL = 6
4680 sizeRSY = 6
4681 sizeRSY1 = 6
4682 sizeRSY2 = 6
4683 sizeRX = 4
4684 sizeRX1 = 4
4685 sizeRX2 = 4
4686 sizeRXE = 6
4687 sizeRXF = 6
4688 sizeRXY = 6
4689 sizeRXY1 = 6
4690 sizeRXY2 = 6
4691 sizeS = 4
4692 sizeSI = 4
4693 sizeSIL = 6
4694 sizeSIY = 6
4695 sizeSMI = 6
4696 sizeSS = 6
4697 sizeSS1 = 6
4698 sizeSS2 = 6
4699 sizeSS3 = 6
4700 sizeSS4 = 6
4701 sizeSS5 = 6
4702 sizeSS6 = 6
4703 sizeSSE = 6
4704 sizeSSF = 6
4705 )
4706
4707
4708 type form int
4709
4710 const (
4711 _a form = iota
4712 _b
4713 _c
4714 _d
4715 _e
4716 _f
4717 )
4718
4719 func zE(op uint32, asm *[]byte) {
4720 *asm = append(*asm, uint8(op>>8), uint8(op))
4721 }
4722
4723 func zI(op, i1 uint32, asm *[]byte) {
4724 *asm = append(*asm, uint8(op>>8), uint8(i1))
4725 }
4726
4727 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) {
4728 *asm = append(*asm,
4729 uint8(op>>8),
4730 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F),
4731 uint8(ri2),
4732 uint8(ri3>>16),
4733 uint8(ri3>>8),
4734 uint8(ri3))
4735 }
4736
4737 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4738 *asm = append(*asm,
4739 uint8(op>>8),
4740 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4741 uint8(i2_ri2>>8),
4742 uint8(i2_ri2))
4743 }
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) {
4757 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F))
4758
4759 switch f {
4760 default:
4761 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2))
4762 case _f:
4763 *asm = append(*asm, uint8(i3), uint8(i4))
4764 }
4765
4766 switch f {
4767 case _a, _b:
4768 *asm = append(*asm, uint8(m3)<<4)
4769 default:
4770 *asm = append(*asm, uint8(i2_i5))
4771 }
4772
4773 *asm = append(*asm, uint8(op))
4774 }
4775
4776 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4777 if f == _a || f == _b {
4778 r1_m1 = r1_m1 - obj.RBaseS390X
4779 }
4780 *asm = append(*asm,
4781 uint8(op>>8),
4782 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4783 uint8(i2_ri2>>24),
4784 uint8(i2_ri2>>16),
4785 uint8(i2_ri2>>8),
4786 uint8(i2_ri2))
4787 }
4788
4789 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) {
4790 *asm = append(*asm,
4791 uint8(op>>8),
4792 (uint8(r1)<<4)|uint8(m3&0x0F),
4793 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F),
4794 uint8(d4),
4795 uint8(i2),
4796 uint8(op))
4797 }
4798
4799 func zRR(op, r1, r2 uint32, asm *[]byte) {
4800 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F))
4801 }
4802
4803 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) {
4804 *asm = append(*asm,
4805 uint8(op>>8),
4806 uint8(op),
4807 uint8(r1)<<4,
4808 (uint8(r3)<<4)|uint8(r2&0x0F))
4809 }
4810
4811 func zRRE(op, r1, r2 uint32, asm *[]byte) {
4812 *asm = append(*asm,
4813 uint8(op>>8),
4814 uint8(op),
4815 0,
4816 (uint8(r1)<<4)|uint8(r2&0x0F))
4817 }
4818
4819 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) {
4820 *asm = append(*asm,
4821 uint8(op>>8),
4822 uint8(op),
4823 (uint8(r3_m3)<<4)|uint8(m4&0x0F),
4824 (uint8(r1)<<4)|uint8(r2&0x0F))
4825 }
4826
4827 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) {
4828 *asm = append(*asm,
4829 uint8(op>>8),
4830 (uint8(r1)<<4)|uint8(r2&0x0F),
4831 (uint8(b4)<<4)|uint8((d4>>8)&0x0F),
4832 uint8(d4),
4833 uint8(m3)<<4,
4834 uint8(op))
4835 }
4836
4837 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4838 *asm = append(*asm,
4839 uint8(op>>8),
4840 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4841 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4842 uint8(d2))
4843 }
4844
4845 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) {
4846 *asm = append(*asm,
4847 uint8(op>>8),
4848 (uint8(r1)<<4)|uint8(r3&0x0F),
4849 uint8(ri2>>8),
4850 uint8(ri2))
4851 }
4852
4853 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) {
4854 *asm = append(*asm,
4855 uint8(op>>8),
4856 uint8(l1),
4857 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4858 uint8(d2),
4859 uint8(op))
4860 }
4861
4862 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4863 dl2 := uint16(d2) & 0x0FFF
4864 *asm = append(*asm,
4865 uint8(op>>8),
4866 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4867 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4868 uint8(dl2),
4869 uint8(d2>>12),
4870 uint8(op))
4871 }
4872
4873 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4874 *asm = append(*asm,
4875 uint8(op>>8),
4876 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4877 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4878 uint8(d2))
4879 }
4880
4881 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) {
4882 *asm = append(*asm,
4883 uint8(op>>8),
4884 (uint8(r1)<<4)|uint8(x2&0x0F),
4885 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4886 uint8(d2),
4887 uint8(m3)<<4,
4888 uint8(op))
4889 }
4890
4891 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) {
4892 *asm = append(*asm,
4893 uint8(op>>8),
4894 (uint8(r3)<<4)|uint8(x2&0x0F),
4895 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4896 uint8(d2),
4897 uint8(m1)<<4,
4898 uint8(op))
4899 }
4900
4901 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4902 dl2 := uint16(d2) & 0x0FFF
4903 *asm = append(*asm,
4904 uint8(op>>8),
4905 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4906 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4907 uint8(dl2),
4908 uint8(d2>>12),
4909 uint8(op))
4910 }
4911
4912 func zS(op, b2, d2 uint32, asm *[]byte) {
4913 *asm = append(*asm,
4914 uint8(op>>8),
4915 uint8(op),
4916 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4917 uint8(d2))
4918 }
4919
4920 func zSI(op, i2, b1, d1 uint32, asm *[]byte) {
4921 *asm = append(*asm,
4922 uint8(op>>8),
4923 uint8(i2),
4924 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4925 uint8(d1))
4926 }
4927
4928 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) {
4929 *asm = append(*asm,
4930 uint8(op>>8),
4931 uint8(op),
4932 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4933 uint8(d1),
4934 uint8(i2>>8),
4935 uint8(i2))
4936 }
4937
4938 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) {
4939 dl1 := uint16(d1) & 0x0FFF
4940 *asm = append(*asm,
4941 uint8(op>>8),
4942 uint8(i2),
4943 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F),
4944 uint8(dl1),
4945 uint8(d1>>12),
4946 uint8(op))
4947 }
4948
4949 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) {
4950 *asm = append(*asm,
4951 uint8(op>>8),
4952 uint8(m1)<<4,
4953 (uint8(b3)<<4)|uint8((d3>>8)&0x0F),
4954 uint8(d3),
4955 uint8(ri2>>8),
4956 uint8(ri2))
4957 }
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) {
4970 *asm = append(*asm, uint8(op>>8))
4971
4972 switch f {
4973 case _a:
4974 *asm = append(*asm, uint8(l1_r1))
4975 case _b, _c, _d, _e:
4976 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F))
4977 case _f:
4978 *asm = append(*asm, uint8(l2_i3_r3))
4979 }
4980
4981 *asm = append(*asm,
4982 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F),
4983 uint8(d1_d2),
4984 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F),
4985 uint8(d2_d4))
4986 }
4987
4988 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) {
4989 *asm = append(*asm,
4990 uint8(op>>8),
4991 uint8(op),
4992 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4993 uint8(d1),
4994 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4995 uint8(d2))
4996 }
4997
4998 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) {
4999 *asm = append(*asm,
5000 uint8(op>>8),
5001 (uint8(r3)<<4)|(uint8(op)&0x0F),
5002 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
5003 uint8(d1),
5004 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
5005 uint8(d2))
5006 }
5007
5008 func rxb(va, vb, vc, vd uint32) uint8 {
5009 mask := uint8(0)
5010 if va >= REG_V16 && va <= REG_V31 {
5011 mask |= 0x8
5012 }
5013 if vb >= REG_V16 && vb <= REG_V31 {
5014 mask |= 0x4
5015 }
5016 if vc >= REG_V16 && vc <= REG_V31 {
5017 mask |= 0x2
5018 }
5019 if vd >= REG_V16 && vd <= REG_V31 {
5020 mask |= 0x1
5021 }
5022 return mask
5023 }
5024
5025 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) {
5026 *asm = append(*asm,
5027 uint8(op>>8),
5028 (uint8(v1)<<4)|(uint8(x2)&0xf),
5029 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5030 uint8(d2),
5031 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
5032 uint8(op))
5033 }
5034
5035 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) {
5036 *asm = append(*asm,
5037 uint8(op>>8),
5038 (uint8(v1)<<4)|(uint8(v2)&0xf),
5039 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5040 uint8(d2),
5041 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
5042 uint8(op))
5043 }
5044
5045 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) {
5046 *asm = append(*asm,
5047 uint8(op>>8),
5048 (uint8(v1)<<4)|(uint8(v3_r3)&0xf),
5049 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5050 uint8(d2),
5051 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0),
5052 uint8(op))
5053 }
5054
5055 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) {
5056 *asm = append(*asm,
5057 uint8(op>>8),
5058 (uint8(v1)<<4)|(uint8(v2)&0xf),
5059 0,
5060 (uint8(m5)<<4)|(uint8(m4)&0xf),
5061 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
5062 uint8(op))
5063 }
5064
5065 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) {
5066 *asm = append(*asm,
5067 uint8(op>>8),
5068 (uint8(v1)<<4)|(uint8(v2)&0xf),
5069 uint8(v3)<<4,
5070 uint8(m5)<<4,
5071 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
5072 uint8(op))
5073 }
5074
5075 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) {
5076 *asm = append(*asm,
5077 uint8(op>>8),
5078 (uint8(v1)<<4)|(uint8(v2)&0xf),
5079 uint8(v3)<<4,
5080 (uint8(m6)<<4)|(uint8(m5)&0xf),
5081 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
5082 uint8(op))
5083 }
5084
5085 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) {
5086 *asm = append(*asm,
5087 uint8(op>>8),
5088 (uint8(v1)<<4)|(uint8(v2)&0xf),
5089 (uint8(v3)<<4)|(uint8(m5)&0xf),
5090 uint8(m6)<<4,
5091 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5092 uint8(op))
5093 }
5094
5095 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) {
5096 *asm = append(*asm,
5097 uint8(op>>8),
5098 (uint8(v1)<<4)|(uint8(v2)&0xf),
5099 (uint8(v3)<<4)|(uint8(m6)&0xf),
5100 uint8(m5),
5101 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5102 uint8(op))
5103 }
5104
5105 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) {
5106 *asm = append(*asm,
5107 uint8(op>>8),
5108 (uint8(v1)<<4)|(uint8(r2)&0xf),
5109 uint8(r3)<<4,
5110 0,
5111 rxb(v1, 0, 0, 0),
5112 uint8(op))
5113 }
5114
5115 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) {
5116 *asm = append(*asm,
5117 uint8(op>>8),
5118 uint8(v1)<<4,
5119 uint8(i2>>8),
5120 uint8(i2),
5121 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
5122 uint8(op))
5123 }
5124
5125 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) {
5126 *asm = append(*asm,
5127 uint8(op>>8),
5128 uint8(v1)<<4,
5129 uint8(i2),
5130 uint8(i3),
5131 (uint8(m4)<<4)|rxb(v1, 0, 0, 0),
5132 uint8(op))
5133 }
5134
5135 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) {
5136 *asm = append(*asm,
5137 uint8(op>>8),
5138 (uint8(v1)<<4)|(uint8(v3)&0xf),
5139 uint8(i2>>8),
5140 uint8(i2),
5141 (uint8(m4)<<4)|rxb(v1, v3, 0, 0),
5142 uint8(op))
5143 }
5144
5145 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) {
5146 *asm = append(*asm,
5147 uint8(op>>8),
5148 (uint8(v1)<<4)|(uint8(v2)&0xf),
5149 uint8(v3)<<4,
5150 uint8(i4),
5151 (uint8(m5)<<4)|rxb(v1, v2, v3, 0),
5152 uint8(op))
5153 }
5154
5155 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) {
5156 *asm = append(*asm,
5157 uint8(op>>8),
5158 (uint8(v1)<<4)|(uint8(v2)&0xf),
5159 uint8(i3>>4),
5160 (uint8(i3)<<4)|(uint8(m5)&0xf),
5161 (uint8(m4)<<4)|rxb(v1, v2, 0, 0),
5162 uint8(op))
5163 }
5164
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